FPGA and SoC software reduces compile times

The release of the Quartus II software version 13.0, delivers the highest levels of FPGA and SoC performance and designer productivity. Users targeting 28 nm FPGAs and SoCs will experience on average a 25 percent reduction in compile times. The most difficult-to-close designs targeting high-end 28 nm Stratix V FPGAs will see compilation times slashed by 50 percent on average compared to the previous software release. Quartus II software v13.0 enables designs targeting Stratix V FPGAs to achieve the fastest Fmax of any FPGA in the industry with a two speed-grade advantage over the nearest competitor.

The release also includes enhancements to the development suite’s high-level C-based, system-/IP-based, and model-based design flows:

SDK for OpenCL opens the world of massively-parallel FPGA-based accelerators to software programmers without FPGA experience. The OpenCL parallel programming model delivers the fastest path from code-to-hardware implementation. Software programmers targeting FPGAs achieve higher performance at significantly lower power compared to alternative hardware architectures.
Qsys system integration tool provides expanded support for ARM-based Cyclone V SoCs. Now Qsys can generate industry-standard AMBA AHB and APB bus interfaces in the FPGA fabric. Further, these interfaces comply with ARM’s TrustZone requirements, allowing customers to partition an entire SoC-FPGA-based system between a secure world for critical system resources and a non-secure world for everything else.

DSP Builder design tool enables system developers to effectively implement high-performance fixed- and floating-point algorithms into their DSP designs. New features include additional math functions with enhanced precision and rounding parameterization, parameterizable FFT blocks for fixed- and floating-point FFTs, more efficient folding capability and improved resource sharing.