Architecturally optimizing compiler for FPGAs

Xilinx, Inc. announced the SDAccel development environment for OpenCL, C, and C++, enabling up to 25X better performance/watt for data center application acceleration leveraging FPGAs. SDAccel, the newest member of the SDx family, combines the industry’s first architecturally optimizing compiler supporting any combination of OpenCL, C, and C++ kernels, along with libraries, development boards, and the first complete CPU/GPU-like development and run-time experience for FPGAs.

First Architecturally Optimizing Compiler for OpenCL, C, and C++
SDAccel’s architecturally optimizing compiler delivers up to 25X better performance/watt compared to CPUs or GPUs and 3X the performance and resource efficiency of other FPGA solutions. SDAccel leverages foundational compiler technology that is utilized by more than 1,000 programmers. SDAccel harnesses the power of this complier and enables software developers to leverage new or existing OpenCL, C, and C++ code for creating high performance accelerators, optimized for memory, dataflow, and loop pipelining in a wide range of data center applications such as compute search, image recognition, machine learning, transcoding, storage compression and encryption.

First Complete CPU/GPU Like Development Experience on FPGAs
With SDAccel, developers can use a familiar workflow to optimize their applications and take advantage of FPGA platforms with no prior FPGA experience. The integrated design environment (IDE) provides coding templates and software libraries, and enables compiling, debugging, and profiling against the full range of development targets including emulation on x86, performance validation using fast simulation, and native execution on FPGA processors. The IDE executes the application on data center-ready FPGA platforms complete with automatic instrumentation insertion for all supported development targets. SDAccel has also been architected to enable CPU/GPU developers to easily migrate their applications to FPGAs while maintaining and reusing their OpenCL, C, and C++ code in a familiar workflow.

The comprehensive SDAccel environment includes the programmer-ready IDE, C-based FPGA optimized libraries, as well as commercial off-the-shelf (COTS) platforms ready for data center use.

SDAccel libraries include OpenCL built-ins, DSP, Video, and linear algebra libraries for high performance, low power implementations. For domain specific acceleration, optimized OpenCV and BLAS OpenCL compatible libraries are available from Xilinx Alliance member Auviz Systems, Initial COTS members include Alpha Data, Convey, Pico Computing with more being added in early 2015.

First Complete CPU/GPU Like Run-time Experience on FPGAs
Only SDAccel supports large applications with multiple programs and CPU/GPU like on-demand loadable compute units. Unique to FPGA solutions, and like CPU/GPUs, SDAccel keeps the system functional during program transitions. SDAccel is the only environment that creates FPGA-based compute units that can load new accelerator kernels while an application is running. Throughout application execution, critical system interfaces and functions such as memory, Ethernet, PCIe® and performance monitors are kept live. On-the-fly reconfigurable compute units allow FPGA accelerators to be shared across multiple applications. For example, operational systems can be programmed to switch between image search, video transcoding and image processing.

Availability
Live SDAccel product demonstrations are available at this week’s Super Computing 2014 conference, booth #3903 in New Orleans. To access the capabilities of SDAccel Early Access release, please contact your local sales representative.Â

Xilinx
www.xilinx.com/sdaccel