The bunch-of-wires (BoW) and Universal Chiplet Interconnect Express (UCIe) standards provide designers with tradeoffs in terms of throughput, interconnect density, delay, and bump pitch. This FAQ compares the performance of BoW and UCIe and looks at how optical interconnects may provide a path to even higher performance interconnects in chiplets. To realize optimal performance for […]
Microcontroller Tips
UBM controllers targeted at data canter and storage management applications
Microchip Technology has introduced the EEC1005-UB2 Universal Backplane Management (UBM) controller family, aimed at enhancing system versatility, ensuring standards-based operation, and offering cost savings in data center and storage applications. These generic and easily configurable UBM devices are designed for use on hard drive backplanes, facilitating storage enclosure management and communication with computing host systems […]
Multi-gigabit asymmetrical Ethernet devices target next-gen vehicles
AVIVA Links, Inc. announced the industry’s first family of multi-gigabit asymmetrical Ethernet devices based on the Automotive SerDes Alliance Motion Link Ethernet (ASA-MLE) draft specification. The new products include Ethernet PHYs, Switches, CSI-2 bridge ICs, and Zonal Aggregators, all of which are optimized for ultra-high bandwidth asymmetric video and control links. These devices are designed […]
JTAG probes support Renesas MPUs
The RZ/V2H is a single-chip MPU designed for next-generation robotics applications that require both vision AI and real-time control capabilities. With the integration of four Arm Cortex-A55 CPU cores, two Cortex-R8 cores, and one Cortex-M33 sub-core, the RZ/V2H can effectively manage both vision AI and real-time control tasks. SEGGER’s J-Link family of debug probes is […]
What is the heterogeneous integration roadmap, and how does it support generative AI?
The heterogeneous integration roadmap (HIR) is an ongoing initiative of the IEEE Electronics Packaging Society. It’s a living document that continues to evolve and expand in response to technological developments like the growth of generative artificial intelligence (AI) and quantum computing. This FAQ starts with a brief overview of heterogeneous integration, looks at the scope […]
Strategic collaboration formed to bring intelligent rendering technologies to graphics-enabled MCUs
Infineon Technologies AG announces its strategic collaboration with Qt Group. This collaboration brings Qt’s lightweight, high-performance graphics framework to Infineon’s graphics-enabled TRAVEO T2G cluster microcontrollers and represents a paradigm shift in graphical user interface (GUI) development. Microcontrollers nowadays offer extensive graphical capabilities that enable compact designs, cost-efficiency, and lower power consumption. With features such as […]
Automotive SoC offers advanced security and communications for vehicle interfaces
Infineon Technologies AG has launched the new Automotive PSoC 4100S Max family. This microcontroller device family expands Infineon’s portfolio of CAPSENSE-enabled Human Machine Interface (HMI) solutions for automotive body/HVAC and steering wheel applications by delivering higher flash densities, GPIOs, CAN-FD, and HW-Security. The Automotive PSoC 4100S Max with fifth-generation CAPSENSE technology offering 10x higher sensitivity […]
Next-gen wireless chips set to meet upcoming cyber-protection standards
STMicroelectronics has revealed the next generation of its short-range wireless microcontrollers. These innovative, all-in-one components enable wearables and smart objects including smart home devices, health monitors, and smart appliances to become ever more miniaturized, easy to use, secure, and affordable. Short-range wireless technologies like Bluetooth LE, Zigbee and Thread (popular in smart meters and smart […]
How does the open domain-specific architecture relate to chiplets and generative AI?
The Open Domain-Specific Architecture (ODSA) is a project within the Open Compute Project (OCP) community to establish open physical and logical die-to-die (D2D) interfaces for chiplets. The goal is to democratize the design and use of chiplets for domain-specific high-performance computing (HPC) applications like generative artificial intelligence (AI). Domain-specific architectures (DSAs) are an emerging approach […]
How do heterogeneous integration and chiplets support generative AI?
Chiplets are here, and more are coming. They can overcome the yield limitations of large ASICs, support a mix-and-match strategy for heterogeneous semiconductor IPs and multiple process nodes, improve thermal performance, and speed time to market. They are being used in a range of high-performance computing (HPC) applications, notably generative artificial intelligence (AI) and machine […]