Cadence Design Systems, Inc. announced that its tools and IP have been optimized to support the new Arm Neoverse N1 platform to accelerate the transformation of a scalable cloud-to-edge infrastructure. To ease adoption, Cadence delivered a 7nm full-flow digital implementation and signoff Rapid Adoption Kit (RAK), collaborated with Arm to ensure the Cadence Verification Suite and its engines improve designer throughput, and integrated Cadence DDR4 PHY IP, CCIX IP and PCI Express® (PCIe) 4.0 PHY IP. Additionally, the Neoverse N1 System Design Platform (SDP), based on the Neoverse N1 platform and Cadence IP, was implemented and verified using Cadence tools to support Cache Coherent Interconnect (CCIX) for asymmetrical compute acceleration.
The RAK for Neoverse N1 includes the Cadence full-flow digital implementation and signoff tools that utilize Arm 7nm POP IP libraries. The comprehensive Cadence RTL-to-GDS flow enables customers to accelerate physical implementation and signoff to speed time to market. The RAK also includes comprehensive documentation and scripts outlining how customers can achieve optimal power, performance and area (PPA) goals with new devices. The tools in the flow include the Innovus Implementation System, Genus Synthesis Solution, Conformal Equivalence Checking, Conformal Low Power, Tempus Timing Signoff Solution and the Quantus Extraction Solution.
Cadence delivered a full verification and emulation suite to support the Neoverse N1 platform including Xcelium Parallel Logic Simulation Platform, Palladium Z1 Enterprise Emulation Platform, JasperGold Formal Verification Platform, vManager Planning and Metrics, Perspec System Verifier and the Cadence Verification IP (VIP) portfolio with the Cadence Interconnect Workbench. The powerful combination of the Cadence Verification Suite and its engines improve verification throughput for engineers creating Neoverse N1-based designs.
Cadence DDR4 PHY IP, CCIX IP and PCIe 4.0 PHY IP have been integrated and proven in silicon with the Neoverse N1 platform, driving key I/O interfaces to peak levels of performance. Arm selected the Cadence IP for the integration due to its strong feature set and maturity with silicon proof-points at 7nm.
Neoverse N1 SDP
Cadence also collaborated with Arm on the delivery of the Neoverse N1 SDP. The N1 SDP is based on the Neoverse N1 platform and Cadence DDR4 PHY IP, CCIX IP and PCIe 4.0 PHY IP that enables asymmetrical compute acceleration via CCIX for application areas like machine learning / artificial intelligence (AI), 5G and analytics. A full Cadence tool flow was used to implement and verify the SDP, and customers can begin software development immediately and shorten overall time to market.