By Chris Francis
Most of my design is for battery operated equipment, requiring low power devices. While I have used a lot of CPLDs and FPGAs over the years, most devices available are not usually “low power” so you have a limited choice. Philips (now NXP) did the CoolRunner CPLDs which were sold to Xilinx and have been updated to form the CoolRunner-II but they are quite dated now. I was using them 15 years ago and they are probably older than that. As an example of the power consumption, the XC2C256 with 256 macrocells has a typical standby current of 33µA at 1.9V and dynamic current of 27mA at 50MHz.
However, with battery operated equipment I would like standby consumption an order of magnitude less than that. Microcontrollers with sub-microamp standby currents are now common and with watchdogs taking less than 1µA. While the CPLD could be powered down, it adds a complexity.
Microsemi IGLOO Nano
Previously known as Actel, Microsemi’s offering in the low power stakes is the IGLOO nano FPGA. These have the “flash freeze” mode which maintains registers and would typically take 12µA at 1.5V for a 512 macrocell device AGLN060 although that is dependent on the I/O and other configuration details. “Flash-Freeze” mode can be as low as around 3µA.
Dynamic power of the IGLOO Nano is design dependent like any other FPGA but uses around 5 to 10mA for the 512 macrocell AGLN060 at 1.2V for a typical design at 50MHz, based on their power calculator spreadsheet. This compares very favorably with the CoolRunner-II.
This brings me to the relatively new Lattice iCE40 FPGA. Targeted at “mobile” products claiming low power and small size, how does it stack up? Like the IGLOO, there is a reasonable range of sizes of device. It comes in three ranges, the LP low power series, the LM with embedded IP and HX high performance. The IP in the LM series mainly consists of SPI/I≤C interfaces. The LP, low power devices have a typical static current of 100µA for a 640 macrocell device so are not very low power when not clocked, even beaten by the CoolRunner-II. The 384 macrocell device has 21µA static current which is not so bad but still a lot more than the IGLOO nano though. The lower current of the 384 macrocell iCE40 is because it doesn’t have RAM whereas the Microsemi IGLOO AGLN060 has 18k bits. The only way to find out the dynamic current seems to be to download the iCEcube2 design software and actually create a valid design. A simple multiple counter test running at 50MHz in the LP1k using just over 700 DFFs resulted in an estimated 8.25mA of current at 1.2V. This seems similar to the IGLOO Nano although without creating an identical design for each IC it is difficult to pick a clear winner.
One useful feature of the iCE40 is the inclusion of RAM on all but the smallest device. The LP640 has 32K bits, for example.
Low power, battery operated designs often need to be small – mine certainly do. Unfortunately FPGAs with a larger core usually come in larger packages. This is to accommodate more input/output pins rather than due to larger die size but forces you to have a large package and large number of pins whether you need them or not. It has resulted in me having to ignore the majority of the pins along two edges to squeeze the chip onto a small PCB in the past, as shown below:
That is a 22mm IC on a 28mm wide PCB. While smaller packages are now available, it seems that they often still try to give a large number of I/O pins in a small package instead of a smaller number of pins in a small package. The iCE40 seems to be an improvement in that regard. Whereas with the CoolRunner-II the smallest package you can get the 512 macrocell device in is a PQ208 which is over 30mm square, the 1280 macrocell iCE40 can be bought in 16WLCSP package which is only 1.4×1.5mm. It has only 16 pins so maybe is a little extreme but is also available in various packages up to 6x6mm 121csBGA (or 5x5mm 121ucBGA). An 84 pin QFN at 7x7mm makes a simpler PCB option for a reasonable size. The Microsemi IGLOO nano options for 1024 macrocells start at CS81 at 5x5mm so if space is tight the iCE40 gives a lot more choices. It is only when you get down to 256 macrocells with the IGLOO that you can get smaller packages although not much smaller because other than the UC81 at 4x4mm the lower pin count devices are QFN and actually larger than the CS81.
The Xilinx parts are expensive, starting at $44.10 for the XC2C512!
The Microsemi AGLN125 (1024 macrocells) starts at around $10.60
The Lattice iCE40 LP1k is $3.90 to $5.40 depending on package (and hence the pincount) so price looks pretty competitive against the competition.
The iCE40 seems to lose out in the static power consumption compared to the Microsemi IGLOO but wins on pin count, size and cost. It seems to be similar for dynamic power consumption as well but would need a complete design for both the IGLOO and iCE40 to find out for certain. The Xilinx is probably only really for existing designs as it seems to have nothing unique to offer and is expensive and large. Altera and Xilinx seem to really be chasing the bigger, better, faster devices rather than the small, low power portion of the market. The iCE40 is a welcome new addition to the lower power market, and if they could get the static power down a bit would be a clear winner.