We often come across designs needing an operational amplifier (op amp) and confoundedly ask, where can I source that pesky negative supply? The quest for a cost-effective, simple and flexible solution often descends down a path of topologies and options that can be cumbersome and never quite straightforward. This article covers the quintessential inverting buck-boost topology that makes quick negative output voltage designs possible from virtually any buck converter available. We can then apply this to any of our op amp, memory or amplifier circuits that come our way.

**Introduction**

It often comes as no surprise that when a good design idea hits, there usually comes an analog component inflexible about a negative input power rail requirement. This is usually an operational amplifier (op amp), but also can be memory ICs, RF amplifiers, or on a much larger scale, magnetrons. We seldom think about the power requirements, opting instead to focus on tackling the problem at hand. As engineers and tinkerers we pride ourselves on focusing on one challenge at a time with the intention of eventually reaching the bigger picture. More often, however, a bird’s eye view of the system is missed entirely or thought about too late in the process – which creates new problems.

With an amplifier comes the primary need to look first at the system’s major aspects. From a power stand point, we know a positive rail is easy to source. Based on the sensitivity of the design, we make decisions on where this should come from. For basic designs and those requiring an electromagnetic interference (EMI) free environment, this tends to be a low-dropout regulator (LDO). However, with the advent of synchronous regulators, this trend is quickly shifting. With μA quiescent currents and vastly superior efficiencies, this really aids in synchronous regulators becoming the ideal power converter of choice.

**The challenge**

We still have the task of designing a negative rail, which is not inherently straightforward. It seems simple to use a battery with the terminals reversed. However, as the battery starts to discharge, the voltage across its terminals begins to decline and eventually falls out of favor with the op amp. Also, depending on the way the circuit is designed, achieving even battery wear during the course of its use is hard and this might not be ideal. Sourcing this voltage from an inverting regulator topology seems to be the best way forward. For one, it is willing to accept a wide range of voltages at its input terminals, eliminating the need for undesirable battery arrangements. Second, it can be driven off of the positive rail, keeping power circuits’ clutter-free and space-efficient.

Now that we’ve settled on using an inverting topology, which do we chose? A Ćuk converter relies on a custom converter, which adds cost and complexity. Whereas a flyback design requires a transformer, adding both space and cost. An inverting regulated charge pump is ideal for less than –5 V outputs based off of a single Lithium-Ion (Li-Ion) battery, but quite impractical everywhere else.

There is a fourth seldom considered approach, the inverting buck-boost. While power designers are well versed with the buck topology, the simple trick of swapping V_{OUTPUT} and ground can bring a whole new topology to life. Moreover, you can easily re-purpose components used on the positive rail, save for an inductor and maybe a few resistors. This can come in quite handy and I will show you how to quickly design a negative rail.

For our example, we use the LM46002, a SIMPLE SWITCHER Wide-V_{IN} synchronous buck converter from Texas Instruments, capable of handling inputs as low as 3.5 V and up to 60 V. It can handle load currents up to 2 A with peak efficiencies of 95% and comes in an easy to use package optimized for simple layout and low EMI. Furthermore, that comparable LDO will now have to contend with ultra-low quiescent currents of nary a few μA. Texas Instruments also provides an easy-to-use software package called WEBENCH to aid in your design.

**The design**

A deeper look comparing buck and boost topologies side-by-side (Figure 1) reveals the inverting topology has the main energy-storing element, the inductor, connected between the switch node and ground. In the buck topology the inductor is placed at the regulator’s output. In the boost topology the inductor is placed at the regulator’s input.

We take advantage of the fact that the inductor always prevents current from changing instantaneously to provide the output we need. Also bear in mind, the polarity-inverting topology is noisy on the input side and on the output side as well. Hence, these noisy nodes require good capacitive filtering to reduce the ripple voltage. In the polarity-inverting topology, both, the input node as well as the output node require good low ESR bypassing capacitors to minimize voltage ripple and noise.

In these types of circuits, we must distinguish the term system ground from IC ground. The two are not the same in inverting topologies. While the system ground is at 0 V or zero potential, the IC ground is the device’s negative output. Be careful to connect the input supply ground to the system ground, and not to IC ground since the latter is negative and can damage certain supplies.

The circuit design illustrated in Figure 2 is simple. Mentioned here are several key design points that will aid in your design. Throughout our design process flow it is vital to remember that the ground of the device, including the exposed pad, should not be tied to system ground.

In keeping with the bird’s eye view method of system design, let us first specify our design. This involves determining the input rail and negative output voltage we desire. This helps us to validate that the correct buck was chosen.

In our design example, we have a 24-V DC source which is commonly found as an automotive bus (+24 V). We need a regulated +12 V and –12 V power rail to power all the op amps downstream in our circuit design (for example, audio rail application). The +12 V rail is easily done with a traditional buck topology. We will proceed with the –12 V. We scoped out all the current requirements and need 1 A, with some margin already built in. The schematic shown in Figure 2 provides a general layout of what to expect. It also mentions approximate values for the passives to enable a stable inverting design.

Our step-down converter has a maximum input operating voltage, V_{DEVICE(maximum)}, of +60 V. Depending on the negative output we require, only a portion of the +60 V will be available to us as input for our negative rail design. Equation 1 describes the maximum input voltage that can be safely applied:

Here, V_{DEVICE(maximum)} is the device maximum input operating voltage.

With our design spec demanding a –12 V output voltage, the maximum input that can be supplied is +48 V. This is double our input specification, so we now have transient spike protection built in up to +48 V. The minimum is governed by (2):

Here, V_{DEVICE(minimum)} is the minimum input operating voltage. This IC specifies it to be +3.5 V.

A note of caution: do not be fooled by the very low input voltage of the buck you choose. The part will experience truly high input currents. Even a small surge during start-up could destroy the part, if it is started directly into full load at this voltage. Instead, a safer solution is to use an under-voltage lock-out (UVLO) in the form of a voltage divider on the enable pin referenced to your input. This ensures the part doesn’t start up until the minimum voltage has reached a safe level.

The next design element is feedback-divider resistor ratios, which is different for every part. The tolerance varies by manufacturer, too. However, a generally accepted equation is (3):

where, V_{REFERENCE} is the feedback reference voltage for your design.

Now we get to the fun stuff and calculate the duty cycle, D, and output current, I_{OUTPUT}. For an inverting buck-boost, the duty cycle is given by the ratio relationship of the input and output voltages (4):

Where, η is the efficiency of the part specified in the datasheet graph section.

Note that the worst case scenario is given by the maximum duty cycle, D_{MAXIMUM} and is calculated by using the minimum input voltage, V_{INPUT (minimum)}, substituted for input voltage, V_{INPUT}, in the duty cycle equation (4). Assuming +5 V as V_{INPUT} and a V_{OUTPUT} of –12 V, the maximum duty cycle, D_{MAXIMUM, }is 0.75 using the datasheet efficiency value, η of 80%.

Finally, we are left to calculate the maximum output current. In the operation of a synchronous inverting buck-boost, when the high-side FET switch is on, the voltage seen across the inductor is V_{INPUT} and the current ramps up at a rate of di/dt = V_{INPUT}/L. While the high-side FET is switched on, the necessary load current is provided by charge stored in the output capacitor.

During the off state, the top side FET turns off and the inductor must reverse polarity to keep the inductor current continuous. The voltage across the inductor is approximately V_{OUTPUT}, and the discharging rate of the inductor current is given by di/dt = –V_{OUTPUT}/L. During this off time, the inductor provides current to the load and simultaneously replenishes energy lost by the capacitor during the on time.

Remember that the average output current cannot exceed the selected part’s rated output. Hence, the available load current is reduced by a factor of (1 – D). From the LM46002 datasheet, the average inductor current is 2 A mentioned as typical value of valley current limit under the electrical characteristics table.

For our design, knowing that the off time is (1 – D) of the switching period, the output current, I_{OUTPUT} is given by (5):

Using this equation, our calculated I_{OUTPUT} is 1.23 A, which more than satisfies our requirement of 1 A.

Now that we have figured out all the final design elements, next we pick our external passives.

**Inductor**

It is important to keep the inductor AC ripple current small. The peak inductor current, which is defined as the average inductor current plus half of the peak-to-peak AC current, should be below the internal control circuit’s current limit. The point at which the circuit operates in discontinuous conduction mode is also governed by the inductor AC ripple current.

Discontinuous operation mode (DCM) occurs when the average current through the inductor is equal to half the peak-to-peak AC current. Generally, this parameter limit is more severe than the preceding current limit.

The inductor ripple current contributes significantly to the output voltage ripple, since the inductor transfers its energy to the capacitor and they work together as a pair. Lower inductor ripple currents provide cleaner output voltages. But if it becomes too low, it affects the signal-to-noise ratio (SNR) detrimentally. This in turn might result in not enough inductor ripple for stable operation.

For any topology, there are significant differences between discontinuous and continuous mode operation. Designs stable in the discontinuous mode may become unstable when increased load current causes them to operate in the continuous mode, during which the feedback loop contains a right-half-plane zero.

Now we know these boundary conditions. The value of inductance, L, in micro Henries can be roughly selected based on (6):

Notice a factor of 0.4 and 0.2. This corresponds to the ripple ratio and is typically 40% as a high limit, and 20% as a low limit. These will vary with the part selected. But as a ballpark figure, these values hold good.

**Capacitors**

*Input capacitors*

This application is stable with almost any combination of ceramic, polymer, tantalum, and aluminum capacitors. However, different buck converters could have their own nuances with capacitors. Therefore, be sure to thoroughly read the datasheet about correct type and implementation. A bypass capacitor is a must from V_{INPUT} to ground and between V_{INPUT} and V_{OUTPUT} on the input side. The bypass capacitor from V_{INPUT} to V_{OUTPUT} is across the device voltage input and its rating must be carefully chosen.

Typically a value of 0.1 μF ceramic should suffice as an input bypass capacitor. For regulator performance, anything between 4.7 μF and 22 μF ceramic should suffice between input and negative output rails. However, the upper limit will vary with the part selected. Finally, a bulk electrolytic capacitor on the input between input and system ground will go a long way towards smoothing out input ripples and providing the necessary ballast for the regulator during high load requirements.

*Output capacitors*

Output capacitors are a bit tricky to figure out and are dependent even more so on the part selected. Ensure correct polarity of the output capacitor, as the output voltage is negative. A well excepted rule is to use twice the recommended buck converter output capacitors for the inverting layout. This can then be adjusted to obtain a compromise between stability and transient response on the output. Equations are hard to provide to figure this out because each part has its own compensation mechanism.

The output capacitor(s), C_{OUTPUT}, should be chosen with care since it directly affects the steady state output voltage ripple, loop stability, and voltage over/undershoot during load current transients.

**Conclusion**The approaches that can be conceived to tackle a negative output challenge are abundant. Hopefully a convincing viewpoint of inverting buck boost over competing alternatives has you clear on one of those approaches. Always remember to plan out the broad facets of your system before tackling the finer details. Here’s wishing you fun on your next perfect inverting design!

**References**

Download the LM46002 datasheet.

**About the author**

Anston Joel Lobo is a system and applications engineer for the SIMPLE SWITCHER™ power group at Texas Instruments. He received his Bachelor of Technology, Electrical and Electronics Engineering from the National Institute of Technology, Warangal, Andhra Pradesh, India. He received his Master of Science, Engineering Management and Leadership from Santa Clara University, California with an emphasis on System Engineering and Analog Electronics. Anston can be reached at ti_anstonlobo@list.ti.com.