Keysight Technologies, Inc. announced PathWave Advanced Design System (ADS) 2023 for high-speed digital (HSD) design with new Memory Designer capabilities for modeling and simulation of next-generation interface standards such as Double Data Rate 5 (DDR5).
As data center throughput climbs, performance expectations of servers and high-performance computing drive the need for new high-density, ultra-fast memory or DDR5 Dynamic Random Access Memory (DRAM). Operating at twice the data rate of DDR4 memory results in shrinking design margins and makes it difficult for hardware designers to optimize printed circuit boards (PCB) to minimize the effects of reflection, crosstalk, and jitter. In addition, lower voltages, higher currents, and new requirements for equalization within the DRAM receiver create signal integrity challenges that are difficult and costly to troubleshoot.
Keysight’s PathWave ADS 2023 for HSD ensures rapid simulation setup and advanced measurements while providing designers critical insights to overcome signal integrity challenges. Its new Memory Designer quickly constructs parameterized memory buses using the new pre-layout builder, allowing designers to explore system trade-offs that reduce design time and de-risk product development for DDR5, Low-Power Double Data Rate (LPDDR5 / 5x), and Graphics Double Data Rate (GDDR6 / 7) memory systems.
Keysight’s PathWave ADS 2023 key customer benefits include: Supports a broad range of next-generation standards: LPDDR4, LPDDR5, GDDR6, GDDR7, HBM2/2E, HBM3, and NAND; Accurately predicts the closure and equalization of the Data Eye: minimizes the impact of jitter, ISI, and crosstalk using single-ended I/O (Input-Output) buffer information specification algorithmic modeling interface (IBIS-AMI) modeling with forwarded clocking, DDR bus simulation, and accurate electromagnetic (EM) extraction of PCB signal routing; Shortens time-to-market with a single design environment that enables pathfinding in pre-silicon digital twins to address current integration requirements such as forwarded clocking and timing, IBIS algorithmic modeling interface (IBIS-AMI) modeling and compliance tests, and future challenges like single-ended Pulse Amplitude Modulation 4 level (PAM4), for exploration of DDR6; Rapidly generates buses via a parameterized pre-layout builder which enables designers to quickly generate wide buses of memory signals and easily create flexible schematics to explore trade-offs; Completes simulation up to 80 percent faster: cloud-based high-performance computing (HPC) utilizes parallel processing to accelerate Memory Designer and EM simulation run times; Automates design-to-test workflows with an easy connection between simulation and measurement domains to enable comparison of the stored data against measured results from physical prototypes;