Arasan Chip Systems expands its IP offering for TSMC’s industry-leading 22nm process technology with the immediate availability of its eMMC PHY IP for SoC Designs on the TSMC 22nm process. The eMMC PHY IP on TSMC 22nm process is seamlessly integrated with Arasan’s eMMC 5.1 Host Controller IP and Software thereby providing customers a Total eMMC IP Solution for TSMC 22nm process.
Arasan offers a comprehensive portfolio of IP for the TSMC 22nm process with its D-PHY v1.1 IP @1.5ghz, D-PHY v1.2 IP @2.5ghz, C-PHY / D-PHY Combo @2.5ghz, and now the eMMC PHY available for this process. All the MIPI PHY’s are available as Tx only or Rx only in addition to the standard Tx/Rx IP.
Compared to its 28nm high-performance compact (28HPC) technology, TSMC’s 22nm ultra-low-power (22ULP) provides 10% area reduction with more than 30% speed gain or more than 30% power reduction for applications including image processing, digital TVs, set-top boxes, smartphones, and consumer products. Meanwhile, the TSMC 22nm ultra-low leakage (22ULL) technology provides significant power reduction crucial for designs in IoT and wearables market segments.
Our Total eMMC IP solution is silicon-proven and also available for TSMC’s 40nm, 28nm, 16nm, 12nm, and 7nm processes. An eMMC HDK containing our TSMC 12nm FFC Test Chip is available for customers who wish to prototype their SoCs.
The eMMC 5.1 Specification from JEDEC, improves the HS400 speeds operating at 3.2Gbps, with “command queuing” – making the data transfers highly efficient by offloading the software overhead into the controller. eMMC 5.1 further improves the reliability of operation by utilizing an “enhanced strobe” at the PHY layer. The eMMC5.1 is backward compatible with the existing eMMC 4.51 and eMMC 5.0 Devices.
Arasan has been a member of the JEDEC eMMC Standards Body since its inception. Prior to eMMC, Arasan offered its solution for Multimedia Cards (MMC) starting in 2001.
