One of the challenges when designing System on Chips (SoC) for wireless applications is optimizing hardware/software partitioning for best flexibility versus power tradeoff. An optimal partitioning is generally easy to achieve for established standards such as 2G, 3G and LTE. However, for standards which are not yet finalized or are still evolving such as 4.5G, 5G, M2M, IoT (LTE-A, 5G, LTE MTC, NB-IoT, EC-GPRS, 802.15.4g, 802.11ah etc.), finding the best tradeoff might be very challenging.
Market requirements will also drive hardware/software partitioning decisions. The importance of flexibility will vary with market segments and product life cycles.
Flexibility is a must in M2M market segments where 10 to 20 year product life cycles are typical and it is necessary to upgrade functionality throughout the product life. However, for consumer products with a two or three year life cycle, cost and power are more important design criteria than flexibility.
For established standards, using hardware accelerators for compute intensive functions will always provide lower power whereas for non-finalized standards a more flexible and programmable solution will reduce the development risk and allow changes until the last minute or even in the field, if required.
Generally the more hardware there is, the longer the development cycle is and the greater is the risk of not getting the design right on the first chip. Conversely, the more software there is, the shorter the development cycle is and the risk could be significantly reduced through software updates at any time during the development cycle. Furthermore, a more power optimized solution with more hardware acceleration can always be designed as a next generation SoC once the market is mature and customers have selected the first generation.
5G poses even greater challenges since computational complexity is two orders of magnitude higher than LTE-A when handling massive MIMO with 64 or 128 antennas, data rates in the 1+Gbps, bandwidth of 100 MHz and frequencies in the 5 to 70GHz range. However, because the standard is still in its infancy, flexibility is essential.
Consequently, new DSP architectures need to be designed which offer very wide data parallelism (much wider than for LTE-A) for larger vector support with a higher number of MACs. This will also require larger fixed-point precision as well as floating-point support for higher dimension matrix operations.
Ultimately, digital front end processing complexity will increase so much, due to the increased bandwidth and massive MIMO, that dedicated DSP engines (also called ASIP) for a specific class of algorithms will be required. Such DSPs are not as programmable as VLIW and Vector DSP but they do offer some level of flexibility within dedicated classes of algorithms.
