By Ian Dennison
As the Internet of Things (IoT) becomes an increasingly competitive market, we should, in 2016, expect new package and board technologies to provide much of the innovation needed for successful IoT products. Since IoT products are driven by the need for the smallest form factor (think wearables) and ultra-low power (for longer battery life), the electronic components for these products must also meet these criteria.
IoT electronics typically integrate radios, CPUs, Flash, RAM, power management units (PMUs), and sensors. For those seeking to also minimize volume costs, all but the sensors can be readily integrated as a system on a chip (SoC). Sensors are typically micro-electro mechanical systems (MEMS), fabricated on different process lines from SoCs, which means separate die for the SoC and MEMS that require physical integration after wafer fabrication. And where significant compute power is required, larger RAM and Flash sizes in the design may dictate separate Flash and RAM die as well.
System-in-package (SiP) technology allows multiple die to be placed within a package molding in a variety of configurations to help solve these form-factor and low-power design challenges (Figure 1). This includes stacks of dies, side-by-side arrangement of dies, and mixtures of the stacks and side-by-side. The die can be connected to each other or to the internal floor of the package, the package substrate, with bond wires. And the package substrate routes the signals out to the external balls of the package. In the stacks, smaller die need to sit on top of larger die so the pads around the die’s edge remain accessible for the bond wires. For the lowest die in the stack, or for the side-by-side dies, flip-chip is the alternative where bumps are added to the pads for direct connection to the package substrate when flipped over.
Enhancing SiPs via silicon-based techniques
It’s good news, then, that SiP technology enables much smaller form factors and interconnect lengths for IoT electronics than is possible with standard parts on a PCB. But the bondwires and interconnects in the package substrate are still physically much larger than the routing on the dies they connect. This means that there are still significant parasitic inductances, capacitances and resistances, with bondwire inductance also a source of ringing, crosstalk, and simultaneous switching noise. Additional silicon-based techniques can be applied inside the SiP to help. For side-by-sides, a silicon interposer within the package can act as a miniaturized PCB with routing widths and spacings much closer to those on the dies, meaning even shorter interconnects and lowered parastics.
For stacked dies, through-silicon-vias (TSVs) within the floorplan of the die allow die-to-die and die-to-package substrate communication when properly aligned up through the dies (Figure 2).
Because TSVs are placed within the floorplan of the die, or at least within the area shared by the dies of the stack, this removes the need to route out to the die’s pads at the edge and back in again. As a result, you get smaller overall interconnect, lower die routing congestion, and further reduced parasitics.
For many IoT applications at the edge, the architecture of IoT allows the compute to be offloaded to the gateway or the cloud, so the edge nodes can be as simple as possible. But other IoT edge applications need real-time responses that just can’t be guaranteed with the communication latencies to the cloud. Collision avoidance between cars is one such example. Such applications demand the compute horsepower to be at the edge. Regardless of where the compute power is found in the architecture for IoT, at the edge, gateway or cloud, these more advanced SiP techniques will likely be part of the solution.
How advanced nodes impact package technologies
Another driver for new package technologies in 2016 will be advanced process nodes for SoCs. Nodes at 20nm and below enable greater digital content, but are increasingly difficult environments for analog and RF design. Analog power and area no longer scale, and increasing transistor variation may demand very different analog and RF design approaches such as digitally assisted analog and RF if the digital and analog must co-exist on a single advanced-node SoC. But as process technologies drive down further to 10nm, 7nm, and 5nm, some may decide to take the digital advantage in advanced nodes while completing their analog in more traditionally analog-friendly nodes such as 65nm. Separate analog and digital dies, each using preferred processes, with integration in an SiP, may be the solution.
Whether using advanced or legacy process nodes, after integrating as much of our IoT system and sensors into SoC and SiP solutions to meet our IoT design form-factor and power challenges, we now need to consider the third fabric, the PCB. Here, we will need to, for instance, integrate the battery, passives, other active devices, and antenna to complete our IoT electronics system.
Flex-rigid PCBs offer rigid board areas populated with components, as well as flexible board areas used primarily for routing between rigid areas. This enables the flexibility often needed in IoT wearables, like wrist bands, to follow contours that just aren’t possible with traditional fully rigid boards. For other applications, we may have extreme limitations on available space, or space that might be irregular, for instance cavities in a small and lightweight drone. Here, parts of a flex-rigid board could be folded back on itself, and multiple foldbacks might result in something cubic, cuboid, or many other three-dimensional forms.
WLCSP supports smaller form factors
Whether boards are folded into something cuboid or are just a single layer, final stack height will be determined primarily by the profiles of the components on the board. Coin batteries are normal for IoT devices for this reason, as are low-profile passives. However, the profile of SoC components can also be reduced through wafer-level chip scale packaging (WLCSP). Here, ball grid arrays are added to the dies of a wafer before the wafer is diced. Once diced, the resulting ‘package’ is very close to the size of the die itself. This saves on the cost and assembly of die into a separate package (normally the provider of the ball grid array for mounting onto a PCB), but WSCLP also helps contribute to stack height and least form factor for IoT designs.
Fully flexible boards offer even more degrees of freedom for IoT product design. Typically, these are sheets of polyester with discrete localized stiffeners under the larger discrete components such as SoCs, instead of the rigid areas of flex-rigid boards. Providing even greater deformation and flexibility, it may be possible one day to have IoT wearables that move more like cloth and could be more seamlessly integrated, hidden, and washed as part of clothing.
SiP technology certainly provides the greatest miniaturization and lowest power for IoT designs, as multiple SoCs, MEMS, and memory dies are physically integrated. But if we are looking for a form factor that spreads the electronics over a wider area, and that is more able to follow contours or be secreted in clothing, then perhaps we could consider fully flexible film populated with WLCSP dies as a more ‘open SiP’ technology that can deform in ways that classical SiP technology cannot.
So, for 2016, we should expect to see a rise in adoption of newer board and packaging technologies like these, to help meet the form factor and low power challenges of IoT product design. And with the array of power, form factor, performance, and cost needs for IoT applications, there is a variety of approaches possible with these board and packaging technologies as well.
About the author
Ian Dennison, Senior. group director of R&D in Cadence’s Custom IC Group, has 30 years of experience in EDA. His primary experience is in analog and mixed-signal design and verification products, with a recent focus on the Internet of Things. Dennison has a bachelor’s degree in computer science from the University of Edinburgh.
Cadence Design Systems, Inc.
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