JEDEC Solid State Technology Association has released JEP200, a new standard detailing test methods for switching energy loss associated with output capacitance hysteresis in semiconductor power devices. This publication, developed by JEDEC’s JC-70.1 Gallium Nitride and JC-70.2 Silicon Carbide Subcommittees, is now available for free download from the JEDEC website.

The increasing adoption of soft switching power conversion topologies has highlighted the need for accurate quantification of energy stored in a power device’s output capacitance, as it impacts power converter efficiency. JEP200 addresses this need by providing standardized test circuits, measurement methods, and data extraction algorithms. The document is applicable to wide bandgap power semiconductors such as GaN and SiC, as well as silicon power transistors and diodes.

This new standard offers power electronics engineers a unified approach to testing new switching energy losses, particularly those related to output capacitance hysteresis caused by displacement currents. The guidance provided in JEP200 enables more precise system optimization, benefiting professionals working on high-frequency power conversion systems.

JEP200 demonstrates the JEDEC JC-70 committee’s ability to respond efficiently to industry requirements. By encompassing GaN, SiC, and Si power devices, this standard assists engineers in addressing design challenges arising from the proliferation of new power conversion topologies.

Power electronics companies worldwide are invited to join JEDEC and contribute to the ongoing work of the JC-70 committee. The next committee meeting is scheduled for November 6, 2024, in conjunction with the WiPDA conference in Dayton, Ohio. For more information or to get involved, contact Emily Desjardins (emilyd@jedec.org) or visit www.jedec.org.