The world’s first design and test workflow solution designed to reduce product development time for Double-Data Rate Dynamic Random-Access Memory (DDR5 DRAM) systems has been developed by Keysight Technologies.
Running at twice the data rate of DDR4, DDR5 DRAM shrinks design margins and makes it difficult for a hardware designer to optimize the printed circuit board (PCB) to minimize the effects of jitter, reflection and crosstalk. Heavily distorted signals can be recovered with decision feedback equalization (DFE), a new addition for DDR5 DRAM, which disrupts the traditional measurement and simulation approaches used for earlier generations of DDR.
Keysight’s comprehensive design and test workflow solution enables hardware engineers to meet their time-to-market window and deliver a high-performance, reliable end-product with:
New transmitter test methods to measure the signal eye diagram after equalization.
New loopback bit-error-rate (BER) receiver tests to validate device and system reliability.
Logic analysis to debug complex DDR5 traffic transactions to identify the source of system instability.
Completing the solution is PathWave ADS Memory Designer for DDR5, a simulation environment that addresses the current challenges faced by designers with the following key features:
Ability to predict performance, optimize a design, and perform virtual transmitter compliance tests, before realizing the first hardware prototype.
Reduced simulation setup time from hours to minutes with new features such as DDR components, smart wires, and an intelligent memory probe.
Increased simulation accuracy for DDR5 by representing receiver equalization with IBIS Algorithmic Modeling Interface (IBIS-AMI) models, enhanced specifically for the requirements of DDR.
“DDR5 is on the horizon, and to secure a competitive edge, organizations are designing their next-generation products to take full advantage of it. However, designing for DDR5 will not be the step-and-repeat of earlier generations. The measurements needed to validate memory systems and the simulation technology needed to predict the performance of memory systems are evolving,” stated Todd Cutler, vice president and general manager of design and test software at Keysight. “Keysight has the technical innovation, breadth of solution and depth of expertise to help our customers get to market faster with their first DDR5 product.”
Keysight’s design and test workflow solution consists of the following product portfolio:
Modeling and simulation (W2225BP)
Probing and interposers
Transmitter test with oscilloscopes and compliance software (Infiniium UXR, N6475A)
Receiver test fixtures
Receiver test solution for loopback Bit Error Rate Testing (M8020A, M80885RCA)
Logic Analysis (U4164A, B4661A)
Power rail probes (N7024A)
Additional information on PathWave ADS Memory Designer is available at the following websites: