More than 10 percent of electricity is lost in power conversion, even as silicon (Si) semiconductors are optimized to their utmost level of efficiency. This loss equates to tens of billions of dollars in wasted energy, along with systems that run hot and require additional cooling mechanisms—meaning more money and physical space spent generating power. Which is why the industry is shifting toward alternative materials, like wide bandgap semiconductors.
Gallium Nitride (GaN) is gaining traction as a more efficient alternative to Si, particularly in high voltage (HV) power applications. According to research firm Yole Développement, the GaN power supply market is expected to exhibit a compound annual growth rate (CAGR) of 79 percent through 2022. This growth will be driven by GaN’s use in markets such as automotive, data center, and renewables.
The adoption pace is generally due to the tech’s “newness”. Si has been the material of choice for many decades. As such, all design and testing methods, understanding of quality and reliability (Q+R), and just general working knowledge in the power engineering space is centered on a material that behaves very differently than GaN.
Yet, markets stand to benefit greatly from GaN’s advantages that average a 40 percent increase in power density, 20 percent reduction in overall system cost, and potential to achieve 99 percent efficiency. Following are three topics that, while often presented as deterrents to GaN adoption, are actually easy to navigate and move beyond.
Fear of the Unknown: GaN Quality + Reliability
GaN is stressed more today than any Si or silicon carbide (SiC) technology. Why? Si is mature, and SiC is considered an extension of Si MOSFETs, given it is a vertical normally-off device with diodes that have been around for nearly 20 years. However, as the market’s newest solution and a viable replacement for both Si and SiC, GaN testing is rigorous, extensive, and goes beyond the norm.
First, GaN platforms can be put through JEDEC and, for the automotive market, AEC-Q101 qualification testing. Though these test methods are designed for Si, they serve as a starting point. Manufacturers then take GaN through extended-JEDEC testing—not technically required to qualify under current JEDEC Si standards—to understand the GaN’s basic Q+R. (Note: the JEDEC Association recently launched the JC-70 committee to establish standards specifically for wide bandgap semiconductors.)
Second, GaN should be subjected to additional testing beyond fundamental quality and reliability to understand its failure modes. This is typically referred to as lifetime or robustness testing. Following are select robustness tests to be considered. Also included are results that can be used to establish a proven Q+R and lifetime baseline. These results were compiled after conducting and repeating these and other robustness tests on large sample sets exceeding the required baseline to ensure the results were valid.
- The High Temperature Operating Life (HTOL) test mimics hard switching conditions and assesses possible interactions that will affect reliability. The tested GaN shows no significant change in performance after HTOL, indicating that its GaN is robust after 3000 hours at a junction temperature of 175°C operating at 300 kHz.
- The High Voltage Off State (HVOS) testing evaluates high field reliability, like High Temperature Reverse Bias (HTRB), but taken to failure. This is where step stress is used by stepping the devices from 600 V to 1800 V with a time between steps of between one minute and one hour. While this takes place the leakage current is monitored to detect device voltage breakdown.
- The High Temperature DC Current (HTDC) test determines failure from trapped charge in the gate region and high on resistance with lower IDSS. Tested GaN shows a median lifetime of >2×107 hours at the peak rated junction temperature of 175°C.
- The High Temperature Gate Bias (HTGB) HEMT-only test uses step stress testing along with other special qualification tests to look at the catastrophic gate insulator failure. Tested GaN shows zero fails at 150°C at 1000 hours.
Fear of the Unconventional: The New PFC Topology
Standard boost and interleaved boost are two of the more common power factor correction (PFC) topologies used within power systems today. True: GaN can be used in these topologies, but the ROI negates the practicality of such a design. Where GaN truly demonstrates its value is in the hard-switched bridgeless totem-pole PFC. Within this topology, GaN’s full effect will be realized: higher performance, higher power density, smaller size, and lower overall system cost.
Until today, most AC to DC power supplies have used analog control for their PFC designs (CCM and CRM). The totem-pole PFC requires the use of digital control that many power supply design houses do not have the capability or resources to achieve.
Interestingly, the bridgeless totem-pole PFC has been around for many years though was unusable with Si MOSFET’s slow reverse recovery body diode and technical challenges prevented its widespread use. So, it was shelved. In a standard boost PFC, the low-side switching device only operates in the forward direction (meaning that there was no reverse current operation through the device, the body diode was always off). With this topology, designs move from a uni-directional control to a bi-directional control methodology where the once HV boost diode is now replaced by a bi-directional GaN FET that needs to be controlled while either being the boost FET or the free-wheeling diode. This requires monitoring zero crossings, the alternative switching control of the high and low side GaN FETs switching from active-switch to synchronous rectification, which requires digital controllers with advanced control algorithms. Being that power electronic engineers have always used analog pre-defined frequency controlled devices, the bridgeless totem-pole offers much more flexibility that requires controllers with FPGA blocks.
Fear of the Known: Inevitable EMI Increases
GaN operates like RF technology capable of higher frequencies and switching speeds than Si and SiC. Further, as GaN inherently offers increased application power density, products built on it can be physically smaller while achieving the same or higher output power (e.g., CORSAIR’s GaN-based AX1600i gaming power supply delivers 6.5 percent more power in an 11 percent smaller form-factor). However, a fast switching technology such as GaN increases the complexity of controlling noise emissions otherwise known as electromagnetic interference (EMI)—particularly with its faster edge rates.
While necessary to avoid sustained oscillation, controlling EMI in GaN designs calls for a level of design precision and techniques not commonly used in the power electronics industry today. Minimizing noise generation, minimizing noise feedback, and dampening the ringing energy resulting from high current/voltage transients can be achieved with recommendations outlined below using a half-bridge switching circuit in Figure 1 as an example.
1. Optimize the PCB layout to minimize external parasitic inductances and associated feedback. Use a large area ground plane for an overall low-noise base potential. Arrange the gate drive circuit on one side and the output circuit on the other side to minimize noise feedback from the output loop to the input loop. Place the driver circuit close to the device’s Gate. Shorten the power loop by arranging the high-side and low-side devices close-by.
2. Use a gate ferrite bead [FB1 in Figure 1] to prevent the high-frequency noise from entering the driver and logic circuits. This bead should be mounted close to the devices’ Gate lead. This is required even for single-ended non-half-bridge designs. GaN manufacturers list gate ferrite bead specifications in device datasheets. Note that TO-247 packages include a built-in gate ferrite bead; therefore an external gate ferrite bead is not needed.
3. Use a DC-link RC snubber [RCDCL in Figure 1]. The DC rail or DC-link, when decoupled with a low-ESR fast capacitor, can be considered a high-Q C-L network at high frequencies (with “L” being the feed inductance of the DC bus). This can interact with the devices at voltage/current transients and lead to ringing. Adding an RC snubber across the DC-link close to the drain pin of the high-side device can effectively absorb the ringing energy, suppressing potential oscillation. This effect is shown in Figure 2 where the high-frequency ringing at 25 A turn-off is substantially damped with the RCDCL. Since this snubber is not inserted at the switching node, it doesn’t add switching loss to the circuit. This is recommended even for single-ended non-half-bridge designs. The practical values of the RCDCL can be 2 sets of 6-10 W/0.5 W SMD resistors in series with a 10 nF/600-1000 V ceramic SMD cap, or 1 set of 3-4 W/1 W resistors in series with a 10-20 nF/600-1000 V cap if space is limited.
4. Add a switching-node RC snubber [RCSN in Figure 1] to further reduce high-frequency ringing and help control di/dt transients at high operation currents. The effect of the RCSN on switching waveform at a switching current >50 A is shown in Figure 3. Unlike the RCDCL, the capacitance of the RCSN does increase switching loss.
