Level Shifting Digital Logic Signals Part 2

I discussed the problem of level shifting logic signals a while ago but I noticed the recently introduced NXP AXP level shifters so thought it was worth revisiting the subject to see if these new devices will really help solving the problem of interfacing the increasingly varied power supply voltages in digital and mixed-signal circuits.  Some devices help avoid the problem by having separate power supplies available for different parts of the chip.  For example the Analog Devices AD7655 analog to digital converter uses a 5V analog section but will interface down to 2.7V for the digital interface.  Digital devices such as FPGAs also have separate core and input/output voltages, usually in blocks so one group of pins can interface with 3.3V and another group interfaces with 2.5V for example.  However, you can still be left with some incompatible voltages which need some additional circuitry to solve.

To recap, the options for level translating, none of which are perfect, range from special purpose level translators such a the PCA9306 for I²C or some low voltage chips which are 5V tolerant such as the or the SN74LVC245A.  Another alternative is to use the simple MOSFET translator for slow signals:

So, are the NXP AXP devices a major step forward?  The first thing I noticed is that they are not all 5V capable.  The T versions are, such as the 74AXP1T57 but the G versions are not, e.g. 74AXP2G3404.  The T versions have dual supply pins where the output supply can be up to 5V but not the input supply.  So, you can interface a 2.5V signal to a 5V system but not the other way round.  The G versions don’t help there because they are not 5V tolerant so cannot interface a 5V signal to a 2.5V system, for example.

If you accept that the T versions cannot have input signals above 2.5V (2.75V absolute maximum) you do have a full matrix of input/output voltages available but obviously not 3.3V or 5V input signals which is unfortunate.

	Input
		1.2V	1.8V	2.5V	3.3V	5V
Output	1.2V	Y	Y	Y	–	–
	1.8V	Y	Y	Y	–	–
	2.5V	Y	Y	Y	–	–
	3.3V	Y	Y	Y	–	–
	5V	Y	Y	Y	–	–

The chips are clearly really meant for low voltages.  The G series are a little different.  They only have one supply voltage which means if you want to translate from a lower voltage to a higher voltage the input logic thresholds are important.  This gives rise to the following permissible input/output matrix:

	Input
		1.2V	1.5V	1.8V	2.5V
Output	1.2V	Y	Y	Y	Y
	1.5V	Y	Y	Y	Y
	1.8V	–	Y	Y	Y
	2.5V	–	–	Y	Y

Where the input and output voltages are the same, the chip can clearly be used but is not level translating in that case.  Some anomalies appear at certain voltage combinations though, because of the input voltage thresholds.  I am assuming here that you set VCC at the desired output voltage.  For example to translate 1.5V to 2.5V you would use VCC as 2.5V and so your logic high threshold would be 1.6V (see specification).  So, your 1.5V signal cannot drive it.

The 1.2V to 1.8V translation is not quite so clear cut – the threshold with a 1.8V supply would be 0.65 x VCC which is 1.17V.  I wouldn’t like to guarantee a 1.2V signal would meet that when you take account of power supply tolerances.  So the G series seem to be more appropriate for going down in voltage (provided the input is not above 2.5V) and the T series for going up in voltage.

So, how do they fare for power dissipation?  The problem with the simple MOSFET translator is that is consumes static power (depending on the logic level) due to the pullup resistors.  In addition, you have dynamic power to consider.  For example, with the values shown earlier using the BSS138, a 3.3V to 5V translation would take 3.3mW at 100kHz and 7.4mW at 10MHz.  That is the total power consumption which is the sum of the power taken from the 5V and 3.3V power supplies plus the power taken from the actual driving logic signal (which must drive the two resistors – one through the MOSFET).  10MHz operation is not that realistic – at that speed the output would never get above 3.3V so isn’t a good level translator.

The 74AXP1T125 power dissipation is quite low when static – typically below 1µA.  It does increase a lot if you hold an input below the input supply.  The example in the datasheet is with VCCI = 2.5V and the input held at 2V where the typical additional supply current is 2µA but a maximum of 100µA at 25C.  This is caused by the PMOS input transistor starting to turn on.  It will not be the case if you are driving the inputs from the correct logic level though.

The dynamic power dissipation needs some calculations based on the formulae and capacitances in the data sheet.  They are dominated by the output capacitance and output supply voltage which is typically 7.6pF at VCCO = 5V.  So, at 10MHz you would have around 1.9mW of dynamic power dissipation assuming no additional load capacitance.  That compares well with the rather crude BSS138 circuit, particularly when you consider that the BSS138 circuit won’t actually be managing to translate the voltage to 5V and is therefore useless – it would need considerably lower resistors to achieve a 5V level shift at 10MHz.  In practice, single MOSFET circuits like that only make sense at low frequencies – the MOSFETs are far too large for a viable circuit.  At 100kHz the 74AXP1T125 would dissipate only 19µW.

In summary, the NXT AXP devices do provide some useful solutions for level shifting but unfortunately leave a few gaps in the combinations of input and output voltage they will cover.  In particular the lack of a 3.3V ability is a bit disappointing.