Legato eliminates the complexity of piecing together point tools for multiple design and verification tasks and can lead to productivity gains of up to 2X when compared with previous point tool offerings, according to Cadence. The Legato Memory Solution’s cohesive design environment automates design steps and lets customers use the innovative Cadence toolset to deliver products to market faster. The solution includes new patent-pending Cadence Super Sweep technology that utilizes existing simulation databases for multi-corner and Monte Carlo analysis, allowing customers to improve both runtime and simulation throughput.
The technology capabilities included with the Cadence Legato Memory Solution improve overall design productivity and are as follows: Bitcell design and verification environment; memory complier design and verification environment; and memory characterization environment.
“Long simulation times and a high rate of inaccuracy have become bottlenecks in the SoC design cycle schedule,” said Tom Beckley, senior vice president and general manager of the Custom IC & PCB Group at Cadence. “The new Legato Memory Solution combines patented technologies interleaved with our existing, proven Virtuoso Liberate MX Memory Characterization Solution, Spectre eXtensive Partitioning Simulator (XPS) and Virtuoso Variation Analysis solutions to improve designer productivity and enable our customers to meet stringent design schedules.”