CEO Wally Rhines, indicated that they are in the process of “…validating the use of our products for successful 3D-IC development with our leading customers who are actively working on products employing multiple die stacking approaches, including the use of interposers, or so-called ‘2.5D,’ and full 3D with through silicon vias (TSVs)”
3D Test Challenges
Since the bottom die in a 3D stack is potentially the only die with external test I/O access, there must be a way to deliver scan test patterns to the upper die in the stack.
Mentor indicates that their new Tessent test solution addresses the three main challenges of 3D-IC testing:
– the need for higher KGD test quality to ensure acceptable package yield