Altera Corporation today announced new programming support for its ARM-based SoCs using industry-standard workflows from MathWorks. Release 2014b from MathWorks includes an automated, highly integrated model-based design workflow optimized for Altera SoCs. Designers using this flow can accelerate their algorithmic designs in Altera SoCs while staying in a high-level programming environment and save weeks of development time.
The highly integrated hardware/software workflow allows programmers to simulate, prototype, verify and implement algorithms that target both the FPGA and ARM processors integrated in Altera SoC FPGAs. The design flow automatically generates the interfaces between the FPGA, the integrated processor system and the software drivers. Targeted support for Altera SoCs is included in two MathWorks code generation products, the HDL Coder and Embedded Coder tools. Using a single development environment, engineers use HDL Coder to generate custom IP cores and configure the programmable logic portion of the SoC, while Embedded Coder is used to generate C/C++ code that runs on the ARM-based hard processor system.
A model-based design environment targeting Altera SoCs accelerates the design process by allowing designers to stay in a familiar design environment without requiring designers to be experienced hardware engineers. Designers leveraging Altera SoCs can accelerate their algorithms in the FPGA portion of the device while running the rest of their design in the ARM processors. Release 2014b includes automated support for Altera’s low-cost Cyclone V SoCs, including automatic programming of Cyclone V SoC development boards.