When new intellectual property (IPs) or a new product hits a new market, concept adoption can be very slow. The case is similar with saving board space without impacting performance when using power management integrated circuits (PMICs). Widely used in smartphones and tablets, PMICs provide great compactness to a solution for powering a system on chip (SOC) without impacting performance. Similar SOCs are being used in industrial applications like human-machine interface (HMI), programmable logic controller, and even infotainment systems – but designers are not ready to adopt these PMICs for their solution. Most designers have a perception that routing power on printed circuit boards (PCBs) is often the biggest challenge when doing layout with PMICs.

Similar SOCs are being used in industrial applications like human-machine interface (HMI), programmable logic controller, and even infotainment systems – but designers are not ready to adopt these PMICs for their solution. Most designers have a perception that routing power on printed circuit boards (PCBs) is often the biggest challenge when doing layout with PMICs.

Some key areas where designers are challenged are power density, component placement, PCB layer count, and signal cross-coupling. With the complex integration of many power sources into a single package in PMICs, PCB design can be even more difficult. This perception is legitimate because PMICs are a new concept in this market, but these problems can be easily solved by paying attention to some key facts that impact power design significantly. This article discusses PCB design and layout strategies for PMICs to manage power density in the harsh environment of industrial environments and automobiles.

Before floor planning the PCB layout, first you need to plan the PCB stack-up. This includes how many layers your PCB will have, and which layers will be dedicated for ground, power and signal layers. A good layer buildup is critical with regards to differential-mode emissions, common-mode emissions, crosstalk, electrical performance, and external noise susceptibility.

Component placement
Component placement is critical to an effective layout. There are several different ways to place components, depending on the application. Each PCB has to be adjusted accordingly, and can have a variety of tradeoffs. There are only a few basic rules that all designs must follow for component placement. A PMIC usually includes integrating several power sources such as buck converters, boost converters, linear drop-out regulators (LDOs), reference voltages, clocks and general-purpose inputs/outputs (GPIOs).

Each power source requires several components such as capacitors, inductors and resistors. It is important to start component placement with the PMIC input pins because the input capacitors are serving as the local power supply, particularly for transient power demand. For example, when a touchscreen in an HMI system is pressed and the system tries to wake up, there is a surge in power consumption that must be supplied by the power management device. Power for that surge comes from the power IC’s input capacitors. Hence, these components need to be placed close to the PMIC.

The main goal is to minimize the parasitic impedance between the capacitor and the input/ground of the IC to maintain the effectiveness of the capacitor’s decoupling mechanism. When board space is limited, prioritize input capacitor placement based on the power source type. Buck converter input capacitors usually have the top priority simply because the input current is switching and discontinuous: the current is changing from zero to full current with a very high edge rate.

Figure 1 illustrates the conceptual current flow of the buck converter power train at steady state. As depicted, both input current (I_VIN) and the ground current (I_GND) are switching currents, while the inductor current (I_SW) is a triangle-shaped waveform. Optimal capacitor placement minimizes voltage spikes on the switch node due to the PCB’s parasitic inductance. Boost converter and LDOs input capacitor placement are relatively less stringent since the input current transient edge rate is slower and is not switching.

Second, give precedence to the PMIC’s output pins. During PMIC component placement, output pin priority is based on the power source. Place components related to the reference blocks first after the input capacitors. Next, place the buck converter inductors on the same layer as the PMIC. Lastly, place buck converter output capacitors after the inductor. If that is not possible, place these components beneath the PMIC on the bottom layer connected with several vias for each component.

There is a slight difference in the placement schemes for boost converters, give precedence to the output capacitors. The boost output capacitor must be placed close to and on the same layer as the IC. This is because the boost current’s output current is switching in nature, which is similar to the buck converter’s input current. The boost inductor can be placed either on the same or opposite side of the PCB relative to the IC. The last power components to be considered should be for the LDOs. Figure 2 shows an example of an effective placement scheme for PMICs.

PMIC signal types
PMICs have several signals categorized as aggressor and static signals. Aggressors are generally the current or voltage signals that are switching at high edge rate, which generally have a high potential to impact signals near them through inductive and capacitive coupling. Typical examples of capacitive coupling sources are switching pins of DC/DC converters, clock signals, and USB D+/D– signals. Examples of inductive coupling sources include buck converter input/ground pins and boost converter output/ground pins, which carry switching current with high edge rate.

Static signals generally don’t carry much current, are not switching or are either high or low level. Typical examples are GPIOs, reference voltages, feedback pins of DC/DC converters, and so on.

In a system that contains significant amount of wired or wireless data communication, data integrity needs to be protected from corruption and interference from other ICs on board, in particular the PMIC. Therefore, the top consideration during layout is to route aggressors away from noise-sensitive signals and to shield the sensitive signal from other aggressor on board. A misconception of layout strategy is that routing the aggressor and static signals on different layers eliminates any potential issues with noise and crosstalk. There is still the potential of crosstalk and noise-degrading device performance, if the signals are close to one another, even if they are on different layers. Figure 3 shows an example of the layout strategy of aggressors and static signals.

Ground signals and planes
Another general layout consideration in PMIC routing is the ground signals and planes. It is important to create a low-impedance ground to the IC, so it is highly recommended that the second layer below the component mounting layer be used as the ground plane. Component via connections, especially the input capacitor, produce low parasitic via connection, which effectively reduces ground impedance. Additionally, the ground plane acts as a shield for capacitive and inductive noise sources on the component mounting layer. Placing a ground (GND) plane on layer two and static signals on layer three of the PCB prevents cross-coupling between the critical signals and the noise sources. An example is shown in Figure 3.

If there are multiple GND planes on the board, these two planes must be connected with multiple vias to maintain the equipotential grounding schemes on the device. Multiple via connections between the ground plane and PMIC input capacitors is critical to ensure the device’s transient response meets the specification. Additionally, high inductance on this path between the ground plane and input capacitor ground pin impacts the DC/DC’s functionality and reliability, especially under transient heavy conditions. A proper via scheme incorporating multiple vias is shown in Figure 4.

Reference voltages routing consideration
In any application, if the reference voltages are not accurate or noisy, all other resources will be impacted. The reference blocks usually require an accuracy range of 0.5% to ensure good performance of their associated blocks. Any high-frequency switching signals or unusual mechanical vibrations on the board, if not taken into account, will impact this accuracy.

Most designers tend to underestimate the importance of the digital core and the reference voltage of the PMICs. Reference voltages and reference GNDs are used in the PMIC as a reference source for the buck converters, LDOs, boost converters and charge pumps. The reference voltage requires a clean ground. Be sure to keep the signals away from the aggressors on the PCB. Hence, use the REFGND ground pin as the ground connection for the reference voltage filter capacitor. REFGND pins must be connected to a dedicated ground plane and connected to main ground at one point (with via, shrunken ground plane, or shunt resistor). The dedicated ground plane should be on the layer under REF components (IREF resistor, BG_REF capacitor) and follows differential nets from the crystal. To prevent disturbance in the ground, define a special restricted area. To isolate REF components, reduce the ground island width between REF components and crystal components.

Buck converter routing consideration
Consider buck converters first when routing the PCB for PMICs, since they are switching power sources and have built-in powertrains inside the IC. The buck converter’s input and ground pins usually carry large and high-frequency switching current, so route them with a thick trace to minimize resistance and inductance. Lower resistance can keep unwanted power loss at a minimum, and low inductance can keep the switching voltage spike small to ensure reliable operation. In some cases, trace inductance as low as 1 nH can still cause issues. Thicker traces enable reliable, efficient operation, and better line transient response for the converter and the system. If the input capacitor is placed close to the pin, it will keep the routing distance minimum making it easier to achieve low-impedance routing. Keeping the routing from the input capacitor to the pin short also helps to reduce the chance of inductive-coupling since the input pin connection is carrying switching current with a very fast edge rate.

The second most important signals in the buck converters are the buck converter’s switching pins. These pins carry high current and can be switching at up to a few MHz with very sharp edge rate and large voltage swing, making it one of the most aggressive noise sources that can capacitively couple to other sensitive signal. The trace needs to be thick and short to keep the resistive power loss low and reduce the chance of coupling to other signal.

The third critical signal on the buck converters are feedback pins. These are sensitive feedback signals that determine the stability of the output voltage. Any instability on this signal causes the buck converter’s output voltage to become unstable. To prevent this, keep this trace away from aggressors and shielded with GND on a different layer than the input pins and DC/DC switching signals. The common aggressors are the switching pins, input pins, and ground pins of the buck converter itself or the signal with switching voltage and switching current. The example of buck routing schemes is shown in Figure 5.

Another consideration with PMICs is the localized ground plane for each buck converter. It is important to keep the GNDs of the buck converter away from the digital GND as they are generally very noisy and can impact the digital logic of PMIC. For this reason, each buck converter must have an isolated small GND plane. The preferred layer is the component mounting layer since it has lowest parasitic impedance between the input/output capacitors and the input/ground pins. The goal is to provide a low-impedance path among the IC, input capacitors, and output capacitors to contain the high-frequency noise before returning to the main ground plane and input plane. If the main component mounting layer is not available to create the localized ground plane, use a layer below the main signal layer, which must connect to the main GND plane with several vias. An example of such routing is shown in Figure 4. Using islands ensures that the converter GND is isolated from the crystal (XTAL) GND, and no noise is transferred between the two. The dotted lines in Figure 6 represent the GND islands below the main signal layer.

Buck controller routing
The routing schemes between buck controllers and converters are very familiar. A typical buck controller block diagram is shown in Figure 6. The major difference between the two is that the high-side drive (HSD) and low-side drive (LSD) FETs are located externally for controllers and are integrated for converters. Since the HSD and LSD FETs are external to the PMIC, consider routing the signals that drive the HSD and LSD FETs. Routing length of the HSD and LSD gate signals must be balanced to ensure on-off timing of the HSD and LSD FETs to achieve the data sheet specified performance. Figure 7 exemplifies routing controller HSD (DRVH) and LSD (DRVL) gate signals, plus boot capacitor signal (VBST). Note that the HSD gate, LSD gate, and boot capacitor signals are switching in nature, with high-edge rates and high-voltage swings, which make them noisy aggressors on the PCB. 

Boost converter routing consideration
Boost converter routing is very similar to buck converter routing, except swapping the routing recommendation of the input side and the output side. Figure 8 depicts the power train block diagram of a buck converter and boost converter. Since the boost converter input current is continuous and not switching while the output current is discontinuous and switching, the output capacitor placement and routing should follow the recommendation of the buck converter input capacitor to minimize routing parasitic inductance and resistance. For the input capacitor routing, minimize routing resistance to avoid unwanted power loss.

Crystal (XTAL) routing consideration
Focus next on the PCB layout for PMICs, which is on the crystal (XTAL) oscillator. The XTAL is used to provide CLK, which is required to power the PMIC. The most important thing to take into consideration for the PMIC XTAL layout is load capacitance; generally a capacitor is present on the crystal’s load recommended by the crystal manufacturer. You need to understand the capacitance of the traces connecting the crystal’s load cap to the PMIC. If trace capacitance is high, this adds to the XTAL’s load capacitor and affects the startup behavior. Slower startup time or failure to startup may cause issues in the PMIC power up. Therefore, traces between XTAL in and XTAL out need to be thin and equal in length. The crystal capacitor must be close to the crystal to reference the crystal to REFGND. Ideally, a dedicated ground island follows differential nets from the crystal.  An example is shown in Figure 9.

Other power resources
In addition to the high-power blocks, there are other power resources in PMICs that are generally used for lower power delivery. Resources like LDOs and charge pumps are prime examples of such resources. Routing LDOs is very simple in nature. The input capacitor takes precedence over the output capacitor. The input capacitor for the LDOs must be placed close to the PMIC and follows the same recommendation as buck converters. You can determine the thickness of the trace connecting the output capacitor to the PMIC by the amount of load current drawn from the PMIC. The larger the current, the wider the trace should be.

Case charge pumps require two tank capacitors to operate. Place both caps equal distance from the PMIC pins, and thickness of these traces should be same. These pins are typically referred to as CP.P and CP.M.

Summary
To obtain maximum performance, follow these recommendations:

1. Before considering component placement, first finalize the PCB layer stack up.
2. Decoupling capacitors must be placed very close to the input pins of the PMIC. For boost converters, it is the output capacitor instead of input capacitor.
3. When components around the PMIC are properly placed, it makes board layout simple.
4. When routing the high-power inputs and outputs for the PMIC, make sure there is IR drop on the signal path is minimized.
5. When routing high-frequency switching signals, make sure the signals are properly shielded.
6. When routing sensitive signals, ensure there is sufficient distance from aggressors and that they are properly shielded with GNDs.
7. Ensure a minimum impedance between decoupling caps GND, PMIC GND pins and GND planes.
8. All GND islands on PMIC must be connected to ensure that signals are equipotential using multiple vias.

References

1. TPS65911 Layout Guidelines, User’s Guide (SWCU080A), Texas Instruments, July 2015
2. Michael Green, TPS65083x Design Guide, Texas Instruments Application Note (SLVA687), February 2014.
3. Schematic and layout checklist for designing with the TPS650860
4. TPS65086x Design Guide, TI User’s Guide, (SLVUAJ9) November 2015
5. Download these datasheets: TPS65911, TPS65218, TPS65910, TPS50860
6. More information about applications that use power management multi-channel IC (PMIC) solutions

About the author
Puneet Sehgal is a strategic marketing manager for the integrated power group at Texas Instruments where he is responsible for product marketing, planning and tracking development. In his spare time Puneet enjoys exploring audio gadgets and music. Puneet received his MBA from the University of Texas, Dallas, and his MSEE from the San Diego State University, California. Puneet can be reached at ti_puneetsehgal@list.ti.com.

Texas Instruments, Inc
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