Introduction
Precision analog-to-digital converters are popularly used in many applications, such as Instrumentation and Measurement, PLM, Process Control, Motor Control, etc. Current SAR ADCs go up to 18-bit or even higher resolution at x-MSPS, while Sigma-Delta ADCs can be 24 or 32-bit resolution at hundreds of kSPS. Users are facing more and more difficulties in limiting the signal chain noise, like in implementing filters, to take advantage of high performance ADCs without limiting the ADCs’ capabilities.
This article discusses the design challenges and considerations associated with implementing analog and digital filters into the ADC signal chain to achieve optimum performance. As shown in Figure 1, the data acquisition signal chain can utilize analog or digital filtering techniques, or even a combination of both. Since precision SAR and Σ-Δ ADCs are commonly sampling within the first Nyquist zone, this article will focus on low pass filters. It is not the intent to address specific low-pass filter design techniques in this article but rather their application in ADC circuits.
Analog Filter vs Digital Filter
The analog low-pass filter can remove high frequency noise and interference from the signal path prior to the ADC conversion avoiding contaminating the signal with aliased noise. It also eliminates the effects of overdriven signals beyond the bandwidth of the filter to avoid modulator saturation. In case of input overvoltage, the analog filter also limits the input current and attenuate the input voltage. Thus, it can protect the ADC’s input circuitry. Noise peaks riding on signals near full scale have the potential to saturate the analog modulator of ADCs. They have to be attenuated with analog filters.
Since the digital filtering occurs after the conversion, it can remove noise injected during the conversion process. In real applications, the sampling rate is much higher than twice the fundamental signal frequency indicated by Nyquist Theorem. So, a post digital filter could be utilized to reduce noise (input noise outside of signal bandwidth, power supply noise, reference noise, noise feed through digital interface, ADC chip thermal noise, quantization noise, etc.) injected during the conversion process by using filtering techniques for higher signal to noise ratio even higher resolution.
Table 1 briefly lists the advantages and disadvantages of analog filter versus digital filter.
Analog Filter Considerations
Anti-aliasing filters are placed in front of ADCs, so these filters consequently are required to be analog filters. An ideal antialiasing filter features unity gain in the passband with no gain variation and a level of alias attenuation that matches the theoretical dynamic range of the data-conversion system in use.
ADCs exhibit different input resistance depending on their architecture, which impacts the input filter design. The following considerations pertain to designing ADC’s analog input filter.
Limitations of RC Anti-alias Filter Interfacing to ADC Front End
- Filter Settling Time for Multiplexed Sampling Signal Chain
A multiplexed input signal typically consists of large steps when switching between channels. In the worst case, one channel is at negative full scale, while the next channel is at positive full scale (see Figure 2). In this case, the input step size will be the full range of the ADC, when the mux switches channels.
One single filter after the MUX can be utilized for the channels, which makes the design simpler and the cost lower. As discussed above, analog filters invariably introduce settling time. Every time the MUX switches between channels, this single filter has to be re-charged to the value of the selected channel, thus limiting the throughput rate. For a faster throughput rate, one filter for each channel in front of the MUX can be an option, but with its associated higher cost.
2. Passband Flatness and Transition Band Limitation versus Noise
Applications encountering high noise levels, especially those with high levels of interference occurring close to the edge of the first Nyquist zone, require filters with aggressive rolloff. However, as it is known that for practical analog low-pass filters, the amplitude rolls down from low frequency to high frequency and has a transition band. More filter stages, or orders, may help improve flatness on in-band signals and render a narrower transition band. However, the design of these filters is complex because they are too sensitive to gain matching to be practical at a few orders of attenuation magnitude. Additionally, any component, such as a resistor or an amplifier, added in the signal chain will introduce in-band noise.
There is a trade-off in analog filter design complexity and performance for some specific applications. For example, in power line relay protection, the protection channels have lower accuracy requirements for the fundamental 50/60 Hz input signal and its associated first five harmonics, than the measurement channels. One single order RC filter could be utilized for the protection channels while a two-order RC filter provides better in-band flatness and more aggressive falloff transition for the measurement channels.
3. Phase Delay and Matching Error for Simultaneous Sampling
Filter design is not just about frequency design; users may also need to consider time domain characteristics and phase response of the analog filters. Phase delay may be critical in some real-time applications. Phase alteration becomes even worse if phase varies according to input frequency. The phase variation in a filter is normally measured in terms of group delay. For a non-constant group delay, a signal spreads out in time, causing a poor impulse response.
For multi-channel simultaneous sampling applications, such as phase current measurement in Motor Control or Power Line Monitoring, the phase delay matching error should also be considered. Make sure the additional phase delay matching errors caused by the filters across multiple channels are negligible, or within the signal chain error budget in the operating temperature range.
4. Component Selection Challenges for Low Distortion and Noise
For low harmonic distortion and low noise applications, users have to select qualified components in the signal chain design. Analog electronics are slightly non-linear, which creates harmonic distortion. In Walsh’s article, he discusses how to select a low distortion amplifier and how to calculate the amplifier noise. Actually, not only active components, such as amplifiers, need to be low THD + N, but also the distortion and noise of passive components, common resistors and capacitors, need to be taken into account.
Resistors exhibit nonlinearity from two sources: the voltage coefficient and the power coefficient. Depending on the application, resistors manufactured by specific techniques, such as thin film or metal resistors, could be necessary in a high performance signal chain. The input filtering capacitors may also add significant distortion if not specified correctly. Polystyrene and NP0/C0G ceramic capacitors can be good alternatives to improve THD if the cost budget allows.
Besides amplifier noise, even resistors and capacitors have electronic noise which is generated by the thermal agitation of the charge carriers inside an electrical conductor at equilibrium. Thermal noise in an RC circuit has a simple expression, as higher R contributes to the filtering requirement as well as to more noise. The noise bandwidth of the RC circuit is 1/(4RC).Two formulas are given to estimate the RMS thermal noise of resistors and small capacitors.
(Boltzmann const) = 1.38065 x 10-23m2kgs-2K-1
T is temperature in K
f is Brick wall filter approximation bandwidth
Figure 4 shows the THD performance effect of an NP0 cap vs an X7R cap on a 18-bit SAR ADC evaluation board: (a) shows the spectrum of a 10 kHz single tone sinewave with C76 and C77 being 1 nF 0603 NP0 caps while (b) shows the spectrum using 1 nF 0603 X7R caps.
Digital Filter Considerations
SAR and Σ-Δ ADCs have been steadily achieving higher sample rates and input bandwidths. Over-sampling a signal at twice the Nyquist rate evenly spreads the ADC’s quantization-noise power into a double frequency band. Then it is easy to design digital filters to band-limit the digitized signal, and then decimate to the desired final sample rate. This technique reduces the in-band quantization error and improves ADC SNR. This technique reduces the pressure on the antialiasing filter by relaxing filter roll-off. Oversampling techniques reduce the demands on the filters, but requires higher-sample-rate ADCs and faster digital processing.
1. Actual SNR Improvement utilizing an Over-sampling Rate on an ADC
Utilizing oversampling and a decimation filter, the SNR improvement can be derived from the theoretical SNR for an N-bit ADC: SNR=6.02×N+1.76 dB + 10*log10[OSR], OSR = fs / (2*BW). Note that, this formula only applies to ideal ADCs in which there is only quantization noise.
Many other sources introduce noise into ADC conversion codes. For example, there is noise from the signal source and signal chain components, chip thermal noise, shot noise, noise in power supplies, noise in the reference voltage, digital feedthrough noise, and phase noise due to sampling clock jitter. This noise may distribute uniformly in the signal band, and appear as as flicker noise. Therefore, the actual achieved SNR improvement in the ADC is commonly lower than that calculated in the formula.
2. Dynamic Improvement with Over-sampling
As shown in Figure 6, the 18-bit 5MSPS SAR ADC measured oversampled dynamic range shows a 1 dB to 2 dB degradation from the theoretical SNR improvement calculation. Because the low frequency noise coming from the signal chain components limits the overall dynamic range performance.
3. Taking Advantage of Integrated Digital Filter in SAR and Σ-Δ ADCs
Usually, digital filters reside in an FPGA, DSP or processor. To simplify a system design effort, ADI provides some precision ADCs with integrated post digital filters. For example, some SAR ADCs have a one-order post digital sinc filter for oversampling. It is easily configured by pulling up or down the OS pins or register. Some new Σ-Δ ADCs have not only a traditional sinc3 filter, but also sinc5+sinc1 and enhanced 50 Hz and 60 Hz rejection filters. They can provide a FAST SETTLING MODE (SINC4 + SINC1 or SINC3 + SINC1 FILTER) function.
4. Trade Off Latency with Multiplexing Sampling ADCs
Digital filters have the disadvantage of latency, which depends on the digital filters’ orders and master clock rate. The latency should be limited for real time applications and loop response time. The output data rate in the datasheet is the rate at which valid conversions are available when continuous conversions are performed on a single channel. When the user switches to another channel, additional time is required for the Σ-Δ modulator and digital filter to settle. The settling time associated with these converters is the time it takes the output data to reflect the input voltage following a channel change. To accurately reflect the analog input following a channel change, the digital filter must be flushed of all data pertaining to the previous analog input.
For previous Σ-Δ ADCs, the channel switching speed is a fraction of the data output rate. Therefore, in switching applications such as multiplexing data acquisition systems, it is important to realize that the rate at which conversions are available is several times less than the conversion rate achieved when continuously sampling a single channel.
5. Avoid Aliasing by Decimation with Digital filters
As discussed in many articles, the higher the over-sampling frequency, the easier the analog filter design becomes. When sampling at a higher rate than you need to satisfy Nyquist, a simpler analog filter could be used to avoid any exposure to aliasing from extremely high frequencies. It is difficult to design an analog filter to attenuate a desired frequency band without distortion, but easy to design an analog filter to reject high frequencies with oversampling. Then it is easy to design digital filters to band-limit the conversion signal, and then decimate to the desired final sample rate without losing desired information.
Before implementing decimation, it is necessary to ensure that this resampling will not introduce new aliasing problems. Make sure the input signal follows Nyquist Theorem referring to the sampling rate after decimation.
Conclusion
The challenges and considerations discussed in this article can help the designer implement practical filters to help achieve the objectives of a precision acquisition system. Analog filters have to interface to the non-ideal input structures of SAR or Σ-Δ ADCs without violating system error budgets while digital filter should not cause errors on the processor side. It is not an easy task, and tradeoff must be made in system specifications, response time, cost, design effort, resources, etc.
