Today, advanced process node SoC designs continue to push the envelope of design and implementation complexity, as well as cell instance count. Competitive top-level power, performance and area specifications, coupled with aggressive production timelines, often result in challenging design closure cycles for next-generation SoCs.
A major factor causing tremendous difficulty in design closure at advanced nodes is the increasing dominance of resistivity to the signal timing. Accurate capacitance estimation alone is no longer sufficient for precise and correlated timing analysis at early stages of digital implementation. A paradigm shift to detailed-route-centric place and route technology, where detailed wire/via resistance and signal routing patterns are readily visible to various P&R stages, is needed to alleviate the challenges to design closure.
In addition, many applications, such as mobile, IoT, and consumer devices, require more demanding low power specifications than that of performance and area. To achieve extreme levels of low power consumption, special technologies are required at various stages of the P&R flow, such as placement, CTS, and routing, to ensure design success of power-sensitive applications.
Lastly, variation-aware timing and optimization are now considered basic requirements of advanced node design flows. The inclusion of variation modeling such as Liberty Variation Format views help provide much more accurate variation-aware timing and power modeling, but also increase design complexity significantly.
Addressing these advanced process node SoC design challenges requires a comprehensive approach to digital design closure, encapsulating not only design placement, clock tree synthesis, routing, and all stages of optimization, but also Liberty timing library model production and verification, and its direct impact on the digital flow.
In this webinar, we will cover proven approaches and best practices used by design teams to accelerate design closure schedules for advanced process node SoC design and implementation, using the Aprisa digital place-and-route system and Solido Characterization Suite.
What you will learn:
- Challenges in advanced node digital SoC design and implementation
- Variation modeling considerations in the digital implementation flow
- Impact of .lib accuracy on overall design quality of results
- Detailed route-centric and power-first digital design implementation
- Machine learning methods to verify and generate .libs for digital flow usage
- Solido Characterization Suite