The 28 nm Stratix V GX FPGAs have achieved inclusion on the latest PCI-SIG Integrators List for the PCI Express (PCIe) 3.0 specification (Gen3). They have successfully passed all PCI-SIG compliance and interoperability tests, completing inclusion for Stratix V on all three generations of the Integrators Lists for PCIe. With Cyclone V and Arria V devices included on the 1.1 (Gen 1) and 2.0 (Gen2) lists, Altera’s entire 28 nm portfolio is now certified by the PCI-SIG as PCIe compliant for all three generations.
Altera’s direct memory access (DMA) reference design, constructed for Stratix V users needing to seamlessly and quickly design PCIe Gen3 solutions. Stratix V GX FPGAs feature a hardened protocol stack for PCIe Gen3 applications, demanding the highest in bandwidth, system integration and flexibility, at a reduced cost with lower total power consumption.
The Altera DMA reference design highlights the capabilities of Stratix V designs that require PCIe Gen3x8. By demonstrating peak bandwidth of the theoretical maximum, the reference design shows that Altera’s Gen3 solution can preserve almost all the bandwidth available in Gen3 systems or at Gen3 data rates. Also, by demonstrating simultaneous read/write at upwards of 11 GB/sec, the design shows how much bandwidth a user can take advantage of in a real-world implementation. Features of the DMA reference design include:
- Linux driver that works with the example design
- Peak throughput (142 cycles of 256-bit at 250MHz)
- 7.1 GB/s: back to back Tx Memory Write 256 Byte payload
- 7.0 GB/s: back to back Rx Read Completion Throughput
- Simultaneous read/write : 11.4GB/sec
Altera Stratix V GX FPGAs for PCIe Gen3
Stratix V FPGAs feature up to four hard PCIe Gen3x8 intellectual property (IP) blocks. The PCIe Gen3 IP blocks support x1, x2, x4 and x8 lane configurations and provide transfer rates up to 8-Gbps per lane, sustaining 2x higher throughput using Gen3 x8 lanes compared to the previous Gen2 x8 version. Hardening the PCIe IP blocks in Stratix V FPGAs delivers a savings of up to 100,000 logic elements when compared to alternative soft implementations. The hard PCIe Gen3 IP blocks embed the PCIe protocol stack into the FPGA and include the transceiver modules, physical layer, data link layer and transaction layer. Stratix V FPGA’s PCIe Gen3 IP targets PCIe Base Specification Rev. 3.0, 2.x, and 1.x.