Mentor announced that TSMC has certified multiple Mentor product lines and tools for the foundry’s recently announced 3nm (N3) process technology. The Mentor offerings now certified for TSMC’s N3 process include the Analog FastSPICE Platform, which provides leading-edge circuit verification for nanometer analog, radio frequency (RF), mixed-signal, memory and custom digital circuits. Mentor has also […]
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EDA FastSPICE, analog/mixed-signal platforms work with new process technologies
Mentor, a Siemens business, announced that its industry-leading Calibre nmPlatform and Analog FastSPICE (AFS) custom and analog/mixed-signal (AMS) circuit verification platform are now qualified for Samsung Foundry’s newest process technologies. Customers can now use these offerings on Samsung’s 5/4-nanometer FinFET processes for the verification and sign-off of production tapeouts for their most advanced IC designs. […]
Spice program upgrades help verify large, post-layout analog designs
Mentor, a Siemens business, announced significant advances in the Analog FastSPICE Platform with the introduction of Analog FastSPICE eXTreme technology for nanometer-scale verification of large, post-layout analog designs. Analog FastSPICE eXTreme includes revolutionary technology that can substantially boost simulation performance, while helping maintain the foundry-certified accuracy required for nanometer-scale analog verification. Analog FastSPICE eXTreme is especially […]
SoC design software helps ID systemic errors early in development
To help integrated circuit (IC) designers achieve design closure faster, Mentor, a Siemens business, today announced the extension of their powerful Calibre Recon technology to the Calibre nmLVS circuit verification platform. Introduced last year as an extension to Mentor’s Calibre nmDRC suite, the Calibre Recon technology is designed to enable customers to rapidly, automatically and […]
IC physical, circuit verification software certified for high-performance process technologies
Mentor, a Siemens business, announced that it has achieved certification for a broad array of Mentor integrated circuit (IC) design tools for TSMC’s industry-leading N5 and N6 process technologies. In addition, Mentor’s collaboration with TSMC has extended to advanced packaging technology, further leveraging Mentor’s Calibre platform 3DSTACK packaging technology to support TSMC’s advanced packaging platforms. […]
End-to-end automation is the next leap forward for DFT
by Jay Jahangiri, Product Manager for Mentor, a Siemens Business, Tessent product family The increase in IC design size and complexity adds a number of new challenges to the design flow, including design-for-test (DFT). One of the most successful changes in design-for-test (DFT) flows in recent years has been the deployment of hierarchical DFT. For […]
A new technique to maximize scan diagnosis throughput
by Jayant D’Souza, product manager Tessent group at Mentor, a Siemens Business Charged with the task of improving yield, product engineers need to find the location of defects in manufactured ICs quickly and efficiently. Typically, they use failing test cycles to perform scan diagnosis, which is then analyzed to reveal the location and root cause […]
IC design software handles 22-nm ultra-low-power process technology
Mentor, a Siemens business, announced that multiple Mentor product lines are now certified for United Microelectronic Corporation’s (UMC’s) 22uLP (ultra Low Power) process technology, including Mentor’s Calibre platform, Analog FastSPICE platform, and Nitro-SoC digital design platform. UMC’s 22nm process features 10 percent area reduction, improved power-to-performance ratio and enhanced RF capabilities compared to the company’s […]
The ABCs of functional verification techniques
By Aijaz Fatima of Mentor, a Siemens business Functional verification is the process of demonstrating the functional correctness of a design with respect to the design specifications. Functional verification does not confirm the correctness of the design specification and assumes that the design specification is correct. It is one of the most challenging steps of […]
How to create and run reusable register-test models
by Matthew Ballance, Mentor, a Siemens Business Register tests are a very useful smoke test at all design levels — from IP to subsystem to SoC. While the built-in register-test sequences in the UVM library are useful at the IP level, capturing register-test intent in a PSS model makes register-test functionality portable from the IP […]
