Synopsys, Inc. today announced a new suite of embedded memory test and repair features for its DesignWare STAR Memory System solution to enable increased test coverage and faster power-on initialization for high-performance automotive, mobile and cloud computing system-on-chips (SoCs). With these new features, designers can achieve a 10x reduction in repair time by eliminating extra cycles and […]
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BIST, repair IP helps automotive SoCs meet functional safety requirements
Synopsys is now making available a validated built-in-self-test (BIST) and repair IP to enable designers to achieve the most stringent levels of functional safety for automotive system-on-chips (SoCs). The complete solution includes the ASIL D Ready Certified DesignWare STAR Memory System, STAR Hierarchical System, and DFTMAX LogicBIST software qualification kit, as well as ARC HS processors, providing test and repair […]
Dev kits cover S32 automotive processing platform
Synopsys, Inc. announced the extension of its multiyear Center of Excellence (CoE) program with NXP and availability of Virtualizer Development Kits (VDKs) for NXP S32 Automotive Processing Platform. VDKs, software development kits using a virtual prototype as the embedded target, enable Tier 1 and OEM companies to start software development and integration and test months […]
Software models multi-level photonic IC designs
Version 2017.09 of the Synopsys RSoft product portfolio software tools for photonic component and optical communication system design includes important new features to streamline and enhance photonic and optoelectronic modeling. The RSoft Photonic Component Design Suite reduces development time with efficient analysis of silicon photonics components at the device, circuit and system levels. The RSoft Photonic System […]
USB 3.2 verification IP and test suite for rapid verification of hosts, devices
USB 3.2 enables new hosts and devices with USB Type-C to be designed as multi-lane solutions, allowing for up to two lanes of 5 Gbps or two lanes of 10 Gbps operation, doubling the data rate over the existing USB Type-C cables. It also supports re-timer enhancements. Synopsys, Inc. now offers what they maintain is […]
Development kit speeds debugging of ARC-based SoCs
Synopsys, Inc. announced the new DesignWare ARC IoT Development Kit to accelerate software development and debug of ARC processor-based system-on-chip (SoC) designs. The ARC IoT Development Kit includes a silicon implementation of the ARC Data Fusion IP Subsystem as well as a rich set of peripherals commonly used in IoT designs such as USB, I3C and PWM. […]
Real-time voice-enhancement tech works with DSP design software
Synopsys, Inc. and Alango Technologies today announced that Alango Technologies’ Voice Enhancement Package (VEP) software has been optimized for Synopsys’ DesignWare® ARC® Data Fusion IP Subsystem. The VEP is a suite of real-time software DSP technologies designed for improving speech recognition performance in voice-controlled multimedia devices. The ARC Data Fusion IP Subsystem is a highly integrated hardware and software IP […]
Logic libraries, embedded memory IP covers 40-nm ultra-low power, 40-nm low-power eFlash designs
Synopsys, Inc. announced its collaboration with TSMC to develop foundry-sponsored DesignWare Foundation IP, including logic libraries and embedded memories, for TSMC’s 40-nanometer (nm) ultra-low power (ULP) eFlash and 40-nm low-power (LP) eFlash processes. Synopsys’ Foundation IP on TSMC’s 40-nm eFlash processes implements unique features that enable designers to reduce power consumption for IoT designs. The logic […]
Low-energy PHY IP achieves Bluetooth 5 qualification
Synopsys, Inc. announced that the silicon-proven DesignWare Bluetooth Low Energy Link Layer IP and PHY IP in industry-standard 40-nanometer (nm) and 55-nm processes have achieved Bluetooth 5 qualification and have been declared compliant by the Bluetooth Special Interest Group. Achieving qualification ensures the robustness of the IP and that it functions as expected within a system-on-chip (SoC). […]
Processors optimize vision software for deep learning applications
Synopsys, Inc. announced a collaboration with Morpho, Inc. to optimize Morpho’s computational photography software for Synopsys’ DesignWare EV6x Vision Processors. Morpho’s Scene Classifier image classification technology uses deep learning algorithms to analyze visual input and automatically apply tags for classification, searchability and organization. Morpho is optimizing their software to take advantage of the EV6x Vision Processors’ […]