Synopsys announced immediate availability of the latest release of its flagship IC Compiler II place-and-route system that includes several new innovative technologies to deliver superior quality-of-results (QoR) and fastest time-to-results (TTR) for the next wave of leading-edge designs across a wide range of vertical markets, including automotive, cloud computing, AI, networking and wireless applications. Continued […]
Compute-intensive IP portfolio for 12-nm FinFET process targets AI, high-end smartphones
Synopsys announced its collaboration with GLOBALFOUNDRIES (GF) to develop a broad portfolio of DesignWare IP, including Multi-Protocol 25G, USB 3.0 and 2.0, PCI Express 2.0, DDR4, LPDDR4/4X, MIPI D-PHY, SD-eMMC, and Data Converters, for GF’s 12-nanometer (nm) Leading-Performance (12LP) FinFET process technology. Synopsys’ DesignWare IP on the GF 12LP process enables designers to implement the latest […]
SoC verification software delivers 5X faster design load and tracing
Synopsys announced a new release of its Verification Continuum Platform with new native integrations across verification tools, enabling up to 5X higher verification performance. Verification Continuum is built from the industry’s fastest engines developed by Synopsys, including Virtualizer™ virtual prototyping, SpyGlass static and VC Formal® verification technologies, VCS simulation, ZeBu emulation, Synopsys HAPS prototyping, Verdi […]
Emulation-based power analyzer sized up billion-cycle software workloads
Synopsys announced its ZeBu Power Analyzer solution for software-driven system-on-chip (SoC) power analysis delivering results 1,000 times faster than traditional simulation-based methods. ZeBu Power Analyzer adds novel, multi-threaded power analysis engines to the industry-leading, high-performance ZeBu Server 4 emulation platform. It allows SoC design teams to systematically analyze power usage of their designs when executing […]
Software verifies NVDIMM-P DDR5/4 memory designs
Synopsys, Inc. announced the availability of the industry’s first verification IP (VIP) for Non-Volatile Dual In-line Memory Module (NVDIMM-P) for DDR5/4. NVDIMM-P is the next-generation storage-class memory for enterprise applications ranging from big data, storage, and in-memory databases, to real-time processing; with challenging requirements of performance, security, and endurance, as well as persistence, reliability, and […]
Display stream compression encoder/decoder gives visually lossless compression
Synopsys announced its DesignWare Video Electronics Standards Association (VESA) Display Stream Compression (DSC) Encoder and Decoder IP for visually lossless compression across display interfaces targeting mobile, augmented/virtual reality, and automotive system-on-chips (SoCs). The new DesignWare VESA DSC IP interoperates with Synopsys’ DesignWare HDMI 2.1, DisplayPort, and MIPI DSI IP to provide a complete display solution […]
Security verification package makes SoCs more bullet-proof
Tortuga Logic announced a partnership with Synopsys to offer a security verification solution that identifies and prevents vulnerabilities in system-on-chip (SoC) designs. The basis of the solution is the combination of security features built into Synopsys’ DesignWare ARC Processor IP and Radix-S, Tortuga Logic’s industry-leading security verification software. Radix-S scans a system’s hardware and software […]
RTL synthesizer delivers faster run times, better-quality power and timing M
Synopsys announced the availability of Design Compiler NXT, the latest innovation in the Design Compiler family of RTL synthesis products. Early adopters have deployed the new technologies in their design flows and are realizing faster runtimes and very tight correlation with Synopsys’ IC Compiler II place-and-route system, leading to shorter, more convergent design cycles. In […]
Machine Learning Inference software facilitates neural network SoC dev
Synopsys announced the availability of the new embARC Machine Learning Inference software library to facilitate development of power-efficient neural network system-on-chip (SoC) designs incorporating Synopsys’ DesignWare ARC EM and HS DSP Processor IP. The embARC Machine Learning Inference (MLI) software library provides developers with optimized functions to implement neural network layer types, significantly reducing processor cycle […]
Security package helps thwart hacking of ARC HS3x/HS4x processors
Synopsys announced the new Enhanced Security Package for Synopsys DesignWare ARC HS Processors, enabling designers to develop isolated, secure environments that help protect embedded systems and software from evolving threats in high-end automotive, storage, and gateway applications. The Enhanced Security Package incorporates a range of features, including integrity protection, multiple privilege levels, and a watchdog […]
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