Synopsys launched its new DesignWare ARC IoT Communications IP Subsystem, an integrated hardware and software solution that combines Synopsys’ DSP-enhanced ARC EM11D processor, hardware accelerators, dedicated peripherals, and RF interface to deliver efficient DSP performance for ultra-low bandwidth wireless IoT (NB-IoT) applications, such as machine to machine communication. The ARC IP Subsystem includes SPI and […]

Synopsys announced availability of the DesignWare ARC HS4x/4xD  Development Kit to accelerate software development for the ARC HS4x/4xD family of high-performance processor IP. The ARC HS4x/4xD Development Kit is a ready-to-use software development platform with support for the Linux kernel and access to the embARC open-source software packages on the embARC website, enabling designers to start software […]

Synopsys announced the availability of the Bluetooth LE Audio LC3 Codec optimized for Synopsys’ DesignWare ARC EM DSP and HS DSP processor IP. The LC3 codec is an important feature of Bluetooth LE Audio, the soon-to-be-released next-generation audio standard defined by the Bluetooth Special Interest Group (SIG) that enables system-on-chip (SoC) designers to efficiently implement […]

Synopsys announced availability of the Bluetooth LE Audio LC3 Codec optimized for Synopsys’ DesignWare ARC EM DSP and HS DSP processor IP. The LC3 codec is an important feature of Bluetooth LE Audio, the soon-to-be-released next-generation audio standard defined by the Bluetooth Special Interest Group (SIG) that enables system-on-chip (SoC) designers to efficiently implement high-quality […]

Synopsys announced the new DesignWare ARC VPX5 DSP and VPX5FS DSP Processor IP that is based on an extended ARCv2DSP instruction set and optimized for a broad range of high-performance signal processing applications, such as RADAR/LiDAR, sensor fusion, and baseband communications processing. The new ARC VPX5 DSP processors implement a configurable, energy-efficient very long instruction word […]

Synopsys announced its DesignWare 112G Ethernet PHY IP on TSMC’s N7 process supporting true long-reach channels for up to 800G networking applications. The DesignWare 112G PHY, based on Synopsys’ silicon-proven 56G Ethernet PHY available in multiple FinFET processes, delivers PAM-4 signaling for more than 35dB channel loss across optical, copper cables, and backplane interconnects. The […]

Synopsys announced the new DesignWare ARC VPX5 DSP and VPX5FS DSP Processor IP that is based on an extended ARCv2DSP instruction set and optimized for a broad range of high-performance signal processing applications, such as RADAR/LiDAR, sensor fusion, and baseband communications processing. The new ARC VPX5 DSP processors implement a configurable, energy-efficient very long instruction word […]

Synopsys announced the Synopsys PrimeECO design closure solution, the industry’s first signoff-driven solution that achieves signoff closure with zero iterations. Signoff closure has emerged as one of the top challenges in digital design implementation, consuming up to 50 percent of the design schedule, mainly driven by rapidly increasing signoff scenarios and physical complexity at advanced […]

Synopsys announced its new native automotive solutions for more efficient system-on-chip (SoC) design. The accelerating evolution of vehicle technologies means that more automotive chips are required to satisfy higher automotive safety integrity levels (ASILs) for autonomous driving and advanced driver-assistance systems (ADAS). Synopsys’ native automotive design solutions enable designers to achieve their target ASILs by […]