To boost productivity and enhance the power, performance, and area (PPA) of advanced electronic designs, Synopsys, Inc. announced the breakthrough golden signoff ECO solution that addresses lengthy engineering design closure times. The Synopsys PrimeClosure solution combines Synopsys’ leading engineering change order (ECO) signoff solutions, Synopsys PrimeECO and Synopsys Tweaker ECO, with breakthrough innovations, delivering the fastest ECO […]
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Security plug-in workswith IntelliJ IDE
Synopsys, Inc. announced the general availability of its Code Sight Standard Edition solution for IntelliJ. Code Sight Standard Edition, which was introduced earlier this year for Visual Studio Code, is a standalone version of the Code Sight plugin for integrated development environments (IDEs) that enables developers to quickly find and fix security defects in source code, open […]
Data analytics portfolio now includes design optimization features
Synopsys, Inc. announced a critical expansion of its EDA data analytics portfolio by introducing the SynopsysDesignDash design optimization solution. As a complementary product to Synopsys’ market-leading Digital Design Family and Synopsys DSO.ai, the award-winning AI-driven design-space-optimization solution, Synopsys DesignDash is a comprehensive data-visibility and machine intelligence-guided design optimization solution that enables unmatched productivity in advanced SoC design. The Synopsys […]
Neural net processing IP includes automatic algorithm partitioning
Addressing increasing performance requirements for artificial intelligence (AI) systems on chip (SoCs), Synopsys, Inc. announced its new neural processing unit (NPU) IP and toolchain that delivers the industry’s highest performance and support for the latest, most complex neural network models. Synopsys DesignWare ARC NPX6 and NPX6FS NPU IP address the demands of real-time computing with ultra-low power consumption for […]
HSM and safety processor help develop automotive SoCs
Synopsys, Inc. announced the availability of its new DesignWare tRoot(TM) Hardware Secure Module (HSM) and ARC SEM130FS Safety and Security Processor IP solutions with integrated functional safety features to accelerate ISO 26262 certification of automotive systems-on-chips (SoCs). The ASIL B compliant tRoot HSM for Automotive adds hardware safety mechanisms for protection against permanent, transient, and latent […]
Chip IP for PCI Express 6.0 includes controller, PHY and verification IP
Synopsys, Inc. announced the industry’s first complete IP solution for the PCI Express (PCIe) 6.0 technology that includes controller, PHY, and verification IP, enabling early development of PCIe 6.0 system-on-chip (SoC) designs. Built on Synopsys’ widely deployed and silicon-proven DesignWare IP for PCIe 5.0, the new DesignWare IP for PCIe 6.0 supports the latest features […]
SoC power-aware emulation verifies power workloads for multi-billion gate designs
Synopsys, Inc. announced the immediate availability of ZeBu Empower emulation system, delivering breakthrough technology for fast hardware-software power verification of multi-billion gate SoC designs. The performance of ZeBu Empower enables multiple iterations per day with actionable power profiling in the context of the full design and its software workload. With ZeBu Empower, software and hardware designers can utilize the […]
Security modules help thwart attacks in HPC SoCs using PCIe 5.0/CXL 2.0 interfaces
Synopsys, Inc. announced the availability of the DesignWare Integrity and Data Encryption (IDE) Security Modules to help designers protect against data tampering and physical attacks in high-performance computing (HPC) SoCs using the PCI Express (PCIe) 5.0 architecture or Compute Express Link (CXL) 2.0 interface. The DesignWare IDE Security Modules protect sensitive data with efficient encryption, decryption, […]
SOC design software features verification planning, memory-aware debug and performance analysis
Synopsys, Inc. announced the availability of the industry’s first Verification IP (VIP) for Compute Express Link (CXL) 2.0 designed for breakthrough performance in data-intensive system-on-chips (SoCs). CXL is the next-generation open standard interconnect that enables an ecosystem for high-speed communication between the CPU and workload accelerators, such as GPUs, FPGAs, and other purpose-built accelerator solutions, as well […]
Chip design software works with 3-nm gate-all-around process technology
Synopsys, Inc. announced the release of the 3-nanometer (nm) gate-all-around (GAA) AMS Design Reference Flow, which provides designers a complete front-to-back design methodology for designing analog and mixed-signal circuits using the Synopsys Custom Design Platform. It has been optimized to provide maximum designer productivity for designers of advanced 5G, HPC, AI, and IoT applications using the Samsung 3nm […]
