The PC-board atomic clock, Part 2: The CSAC design

Atomic clocks have shrunk from room-sized assemblies down to PC-board mountable modules, admittedly with lower performance than their big siblings but still far better than crystal-based timing alternatives.

Engineering is largely about tradeoffs and constraints, and atomic clocks are no exception to this situation. As these clocks are being designed into smaller packages through innovations, in theory, material, physics, manufacturing, and more, the obvious question is: “how good are they?” The answer is simple: as these smaller clocks literally downsize from room size to rack size to module size, and now so-called chip size, there are reductions in basic performance.

But that’s a tradeoff that’s quite acceptable in many applications, especially when viewed in the context of what the higher level of performance enables. Given the availability and maturity of OXCO and TXCOs, the issue is which applications need even higher performance than those crystal units can provide, and with what impact on cost, size, weight, and power (CSWaP). A rough indication of the basic performance clock-performance metric for mechanical (crystal) versus atomic units shows this tradeoff (Figure 1).

Fig 1: The relationship among various clock types with respect to performance is also a function of their combined cost, size, weight, and power metric. (Image: Microchip Technology)

The primary applications for higher-performance clocks are mil/aero requirements related to higher-performance GPS receivers, backpack radios, anti-IED jamming systems, autonomous sensor networks, unmanned vehicles, and underwater sensor systems. These are all situations where better timing improves performance, or where Global Navigation Satellite Systems (GNSS) time signals are physically unavailable, degraded, limited (fewer than four satellites visible), or completely denied.

Addressing this opportunity, Microchip Technology recently introduced the SA65 Chip Scale Atomic Clock (CSAC) (Figure 2). This is not a monolithic IC, but tiny cesium-based atomic-clock module with multiple functional elements mounted to a substrate. The SA65 module measures just 1.6″ × 1.39″ × 0.45″ (approximately 40 × 35 × 11.5 mm), weighs 1.25 ounces (35 grams), and requires under 120 mW of power.

Fig 2: The SA65 is housed in an ordinary-looking metal module measuring 1.6″ × 1.39″ × 0.45″ (approximately 40 × 35 × 11.5 mm). (Image: Microchip Technology)

The SA65 is not a totally new technology but is the successor to SA45 introduced in 2011 (more on this later). The SA65 CSAC provides RF and one pulse per second (PPS) outputs at standard CMOS levels, with short-term stability (called Allan Deviation or Variance, a key clock metric; see References) of 3.0 × 10^–10 over a one-second interval (tau or τ), typical long-term aging of <9 × 10^–10/month, and maximum frequency change of ±3 × 10^–10 over the operating temperature range of –40°C to +80°C.

It also accepts a 1 PPS input that can be used to synchronize the unit’s 1 PPS output to an external reference clock with ±100 nsec accuracy and “discipline” its phase and frequency to within 1 nsec and 1.0 × 10^–12, respectively.

How does the chip-scale SA65 emulate what those larger systems do in a tiny module, although with admittedly lower timing performance than those larger systems? It’s obviously complicated and requires deep atomic-level physics – but that is just the starting point, of course.

In brief, the CSAC is a passive atomic clock, incorporating the interrogation technique of coherent population trapping (CPT) and operating on the D1 optical resonance of atomic cesium. The heart of the CSAC “physics package” is the cesium resonance cell which is fabricated of silicon, loaded with cesium metal and inert buffer gas, and sealed at each end with Pyrex windows, one of which is copper-plated to provide the retroreflection for the folded optics of the cell (Figure 3). The resonance cell uses an optical path which folds on itself for compactness and optical performance.

Fig 3: This cesium cell is the heart of the physics package of the SA65. (Image: Microchip Technology)

In addition to the physics package, the CSAC includes a TXCO, a loop filter, a microwave synthesizer, and a microprocessor (Figure 4). The microwave synthesizer generates 4596.3 MHz with a tuning resolution of approximately 1 × 10^–12.

Fig 4: The complete SA65 includes a TXCO, a loop filter, a microwave synthesizer, and a microprocessor. (Image: Microchip Technology)

The microprocessor serves multiple functions, including implementing the frequency-lock loop filter for the TCXO, optimization of physics package operation, state-of-health monitoring, and command and control through the serial communications port. (Interestingly, both the SA65 and the Stanford Research Systems PRS-10 use the venerable RS-232 interface for bidirectional communication with the rest of the system; older interfaces sometimes take a long time to fade away.)

The RF output from the CSAC is provided by the temperature-compensated crystal oscillator (TCXO), which is buffered by a CMOS logic gate and provided on the CSAC output (pin 12). In normal operation, the frequency of the TCXO is continuously compared and corrected to the ground state hyperfine frequency of the cesium atoms contained within the physics package, which improves the stability and environmental sensitivity of the TCXO by four to five orders of magnitude.

The final part of this article looks at the physics package in more detail and provides some history of the development of the CSAC.

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