Talk about downsizing – researchers at the University of California in Santa Barbara have developed a design for a 50 nanometer square computer, the university announced Oct. 27.
For now, that size is entirely theoretical. It could be managed by a novel kind of logic that enables the computer to process data inside a three-dimensional structure.
“In a regular computer, data processing and memory storage are separated, which slows down computation. Processing data directly inside a three-dimensional memory structure would allow more data to be stored and processed much faster,” said Gina Adam, a postdoctoral researcher and the lead author of the paper.
Her paper, “Optimized Stateful Material Implication Logic for Three Dimensional Data Manipulation,” was published in the journal Nano Research. It calls for a nanoscale 8-bit adder operating in that 50 nanometer-square space using material implication logic. Memristors are also important to the design. Together, this all allows the result of the computation to be immediately stored, cutting down on the necessary space and preventing data loss in the case of unexpected power losses.
Memristors are traditionally built in two dimensions, but creating the three-dimensional block enabled downsizing the blocks to the nano scale. Researchers are now working on other possible applications of nano-scale memristor configurations.
The research into the tiny computer is part of the Feynman Grand Prize challenge, put on by the Foresight Institute in order to put into practice Richard Feynman’s “Plenty of Room at the Bottom,” a theoretical talk on tiny computers.
