Synopsys launched its new DesignWare ARC IoT Communications IP Subsystem, an integrated hardware and software solution that combines Synopsys’ DSP-enhanced ARC EM11D processor, hardware accelerators, dedicated peripherals, and RF interface to deliver efficient DSP performance for ultra-low bandwidth wireless IoT (NB-IoT) applications, such as machine to machine communication.
The ARC IP Subsystem includes SPI and GPIO for RF control and UARTs for logging and host control. The digital front end (DFE) offers a flexible interface to third party RF solutions, such as Palma Ceia’s Release 14-compliant NB-IoT transceiver. The ARC IP Subsystem also contains a base software communications library, peripheral drivers, and application examples. The ARC IP Subsystem delivers the performance efficiency needed for a wide range of IoT applications including smart city, smart agriculture, and industrial automation.
The integrated, ultra-low power ARC EM11D processor combines RISC and DSP capabilities for a flexible architecture that quickly adapts to rapidly changing wireless standards. The EM11D’s zero-latency XY memory architecture implements instruction-level parallelism and single-cycle 16+16 MAC operations for power-efficient data processing. Dedicated hardware accelerators for Viterbi decoding and trigonometric functions provide performance boosts for LTE NB-IoT algorithms while keeping processor frequency requirements to a minimum. Power management, critical to efficient IoT communications, is supported by an on-board power management unit, enabling up to six independent power domains and three unique power modes to support LTE Power Saving Mode (PSM) and Extended Discontinuous Reception (eDRX) modes.
The ARC IoT Communications IP Subsystem includes a baseline communications library, which provides a critical foundation for NB-IoT functions, such as symbol interpolation, FFTs, modulation, and data manipulation. The application examples demonstrate use-cases in a typical Orthogonal Frequency-Division Multiplexing (OFDM) processing chain. The subsystem is supported by Synopsys’ DesignWare ARC MetaWare Toolkit, which includes a rich library of DSP functions, allowing software engineers to rapidly implement algorithms from standard DSP building blocks.