The AC performance of an analog-to-digital converter depends on its architecture.
In part 3 of this series, we discussed the integral nonlinearity (INL) error of an analog-to-digital converter (ADC), noting that gain, offset, and INL error all contribute to the total unadjusted error. This metric provides an overall view of an ADC’s DC performance.
Q: What about the AC performance?
A: The AC performance depends on the ADC’s architecture. Common ones are the delta-sigma[1], successive-approximation-register (SAR), and flash architectures. In this article, we’ll take a look at the last two. First, Figure 1 shows an eight-bit SAR ADC, which, as the name suggests, takes a multiple-step iterative approach to the conversion process.
To begin, the SAR logic writes the binary sequence representing one-half the full-scale (FS) voltage to a shift register—10000000 in this case. A digital-to-analog converter (DAC) converts the binary sequence to an analog voltage, VDAC, which a comparator compares to the input voltage, VIN. If VIN is greater than or equal to VDAC, the SAR logic retains a logic one for the MSB; otherwise, it resets the MSB to zero. The SAR logic then sets the second most significant bit (MSB) of the shift register to 1, and the process repeats until the full output sequence has been calculated down to the least significant bit (LSB).
Q: What’s the S/H symbol on the left?
A: That’s a sample/hold buffer amplifier, which typically has a unity gain. For the SAR device, the conversion process is relatively slow, and the continually varying analog input signal, VINA, may change before the conversion process is complete, leading to inaccurate or ambiguous results. When a control signal is asserted, the S/H amplifier maintains its output at a constant level for a predetermined period, allowing the conversion process to complete. In Figure 2, the blue curve is the analog input, the S/H control is asserted every 2 µs, and the red curve represents the S/H amplifier output.
Q: What’s about the flash architecture?
A: To form an n-bit ADC, the flash architecture uses a string of 2n-1 comparators and a resistor ladder extending from a reference voltage to ground. Figure 3 shows a two-bit flash device with three comparators and four resistors. The resistor values are equal, except for those connected to the reference voltage and ground, which vary depending on the coding scheme, as discussed in part 1. With the configuration shown, each comparator operates simultaneously, and if VIN is less than V0, all comparators are off. As VIN rises, they are sequentially driven positive, until all generate a positive output when VIN exceeds V2.
Q: What are the pros and cons of the SAR and flash architectures?
A: SAR devices are compact and low power — they contain one comparator, a DAC, and some logic. They are, however, comparatively slow, but are useful in data-acquisition systems that monitor slow-moving variables, such as temperature. In contrast, flash devices are fast and find use in applications such as high-speed oscilloscopes. They are, however, relatively large and power-hungry. Note that an eight-bit flash ADC requires 255 comparators.
Q: What’s the purpose of the encoder on the right in Figure 3?
A: The output of the comparators is sometimes called a thermometer code. If you envision an eight-bit flash ADC with a vertical stack of 255 comparators each driving an LED, you can imagine a column of light rising and falling with voltage, just as mercury rises and falls in a thermometer as temperature varies. This coding is not very useful, and the encoder converts it to a binary number. For the two-bit version shown, the only possible outputs are 00, 01, 10, and 11.
Q: What about the AC specifications?
A: Throughput, or samples per second, is the key one. Others include the same ones you’ll find in any circuit, including signal-to-noise ratio (SNR) and signal-to-noise plus distortion ratio (SINAD)[2]. A spec unique to data converters, but based on SNR and SINAD, is an effective number of bits (ENOB). There is a rather famous, and some say infamous[3], equation for calculating an ADC’s SNR as a function of quantization error, and another for calculating ENOB. In the final part of this series on ADCs, we’ll focus on AC specifications, and we’ll discuss those equations, what they mean, and how they were derived.
References
[1] How delta-sigma ADCs work, Part 1, Texas Instruments[2] ADC AC Specifications, Microchip
[3] Taking the Mystery out of the Infamous Formula, “SNR=6.02N + 1.76dB,” and Why You Should Care, Delft University of Technology
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