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What is a PLL for analog signals?

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A phase-locked loop (PLL) for analog signals generates an output with a phase that’s precisely matched to the phase of an input reference. Analog PLLs are widely used in high-frequency applications like communication systems and scientific equipment requiring low jitter and precise synchronization.

This article begins by looking at how PLLs for analog signals operate, briefly compares them with digital PLLs and other PLL architectures, and closes by reviewing PLL application considerations.

A PLL for analog signals consists of three basic elements: a phase detector, a proportional integral derivative (PID) controller (sometimes called the loop filter), and a voltage-controlled oscillator (VCO). It uses negative feedback to ensure that the input reference signal and output follower signal have the same frequency and are in-phase as seen in Figure 1.

Figure 1. Block diagram of a PLL for analog signals. (Image: Zurich Instruments)

PLL operation

PLL operation begins with the phase detector determining the phase difference between the input and output signals. Based on that difference, the PID controller produces a feedback signal to tune the frequency of the VCO. The VCO follows the input signal phase and frequency, generating a precisely matching output signal.

PLL operation can also described as a series of three stages, as illustrated in Figure 2:

  1. Free running refers to the center frequency of the PLL (the frequency of the VCO) when not locked to the input frequency.
  2. Capture is when the input signal is within the PLL’s capture rang,e enabling the VCO to lock to the input frequency.
  3. Phase lock, or tracking, occurs when the VCO has locked onto the input frequency. It will continue to track the input and adjust the output if the operation remains in the PLL’s capture range.
Figure 2. Summary of the three stages of the operation of a PLL for analog signals. (Image: Cadence PCB Solutions)

Types of PLLs

There are several types of PLL architectures available for specific application needs:

Analog PLL (APLL), also called linear PLL (LPLL) described above: APLLs can support high-frequency and high-performance timing applications but are complex to design and may consume more power than digital architectures. APLLs are used in communications systems and scientific equipment.

Digital PLL (DPLL) that use a digital phase detector, digital filters, and an analog VCO: These designs are typically smaller than APLLs.  DPLLs are suited for integration into VLSI designs but can be more susceptible to phase noise than APLLs. DPLLs are common in embedded applications.

All digital PLL (ADPLL) that use all digital components, including the oscillator: ADPLLs overcome the supply voltage limitations of APLLs and are fully customizable. ADPLLs require precise calibration for optimal performance. They are well-suited for use in portable devices like wearables and smartphones.

Table 1. Comparison of some features and benefits of APLLs, DPLLs, and ADPLLs. (Image: Success Bridge)

PLLs can also be implemented in software (SPLL). These designs typically provide the greatest degree of flexibility and are often used in applications like photovoltaic (PV) inverters where the output needs to precisely match the grid frequency, even when confronted with conditions like voltage unbalances, line dips, and other power quality issues.

Application considerations

There are several factors to consider when designing APLLs, including:

  • Balancing loop bandwidth with noise sensitivity because higher bandwidth can increase noise sensitivity. It’s usually recommended that the bandwidth be set to under one-tenth the phase detector frequency
  • The filter in the phase detector needs to be carefully designed to balance noise rejection, bandwidth, complexity, and power consumption to maximize application performance.
  • Several factors can impact stability, including the phase margin that should be kept between 45° and 60°.
  • A high-quality reference can contribute to stability and support a cleaner output with less jitter.
  • Transient response, including settling time and overshoot, need to be balanced to achieve the desired accuracy.
  • Any sidebands caused by VCO tuning voltage ripple can degrade the output.
  • A combination of bandwidth and VCO phase noise can affect phase noise dynamics.

Summary

A PLL for analog signals is a feedback control system that generates an output with a phase that is precisely matched to the input signal’s phase. APLLs are high-performance implementations used in communications systems and scientific equipment. PLLs can also be designed using combinations of digital components and software to optimize the tradeoffs between performance, complexity, size, cost, and power consumption.

References

Digital PLL, All Digital PLL, & Analog PLL: Which has Best PPA for Edge AI, IoT, Aerospace, High-Performance Cloud…?, Movellus
How to Design and Debug a Phase-Locked Loop (PLL) Circuit, Analog Devices
Phase-Locked Loop (PLL) Definition, Intel
Phase-Locked Loops (PLL), Cadence PCB Solutions
Phase-Locked Loops for Analog Signals, Zurich Instruments
Phase-Locked Loops (PLLs) for Analog Signals: Principles, Applications, and Design Considerations, Quarktwin Technology
PLL Design Tips, Cadence PCB Soluions

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