Silicon carbide is a notoriously hard and complex material. Wafer production for fabricating SiC power semiconductors leverages intensive engineering of manufacturing processes, specifications, and equipment to achieve commercial quality and cost-effectiveness.
Necessity and invention
Wide-bandgap semiconductors are changing the game in power electronics, enabling system-level efficiency to move beyond the practical limits of silicon devices and bringing additional technology-specific benefits. In the case of silicon carbide (SiC), thermal conductivity, temperature-withstand capability, and breakdown voltage versus channel thickness are superior to silicon, easing system design and ensuring greater reliability.
Due to their simplicity, SiC’s gestation delivered diodes to the market ahead of MOSFETs. Now, established power-transistor families are entering their fourth and fifth generations as technological progress tightens process control, raises yield, and improves device parameters, including figures of merit like on-resistance per die area.
Demands from growing markets, particularly in the automotive and renewable energy industries (Figure 1), have driven economies of scale that enable SiC devices to offer an affordable and cost-effective solution in a wide range of applications. Railway traction systems, telecom and data-center power, industrial motor drives, and high-power medical equipment such as X-ray machines and MRI scanners leverage SiC to boost efficiency and power density. On the other hand, industrial applications like down-hole drilling equipment rely on the technology for high-temperature operation and ruggedness.
In response to market demands, today’s manufacturing capabilities deliver high product quality and commercial yield thanks to careful engineering beginning at the start of the device lifecycle: producing the SiC ingot from which the bare wafers are sawn and subsequently ground and polished before epitaxy and, finally, device fabrication.
The equipment available to manufacturers has also evolved. SiC foundry work began using small, single-wafer reactors. One advantage of single-wafer processing is that the settings can be highly optimized to achieve the best possible yield, taking advantage of the knowledge accumulated over many years since the beginning of SiC research. However, the processing cost is relatively high for commercial production. More recently, equipment makers have produced multi-wafer reactors that can handle 6-inch and 8-inch wafer diameters. Compared to single-wafer reactors, multi-wafer processing can deliver economies of scale, although uniformity is much more difficult to achieve.
SiC wafer production
The boule is grown by heating it to a high temperature in a vacuum or inert gas atmosphere until sublimation occurs using polycrystalline silicon carbide or a silicon/carbon powder mix as feedstocks. A seed crystal is introduced, and the vapor is cooled, causing SiC molecules to deposit on the seed crystal, forming a larger crystalline structure. Over 200 possible SiC crystal configurations, or polytypes, have hexagonal (H-type) or cubic (C-type) structures. The temperature and pressure under which the crystal is formed, and any impurities present determine which polytype will predominate.
Among possible polytypes (Figure 2), 4H provides the best properties for power semiconductor devices. Its bandgap energy of 3.26 eV and breakdown field strength of 3.5 MV/cm compare with 3.03 eV and 3.0 MV/cm for 6H SiC, yielding superior properties for handling high applied voltages. The 6H polytype is typically used for RF devices. Both types have a thermal conductivity of 4.9 W/mK, far superior to silicon’s 1.31 W/mK, while SiC electron saturation velocities are at least double that of silicon, supporting superior high-frequency performance.
Due to the SiC boule’s extreme hardness, it is sliced into wafers, usually with diamond-encrusted wire saws. The wafers are then ground flat and polished, and the substrate surface is treated to create steps and terraces that promote epitaxial growth. The boule is cut off-axis at a narrow angle, approximately four degrees for 4H polytype wafers, which permits a superior surface finish with longer terrace lengths for epitaxy.
Unlike silicon ingots, which can be grown with close-to-perfect purity and then sliced into very uniformly flat wafers, SiC wafers can contain crystal defects such as basal plane dislocations, micropipes, and screw dislocations. Depending on the type and severity, these defects can cause flaws in the epitaxial layer. Inevitably, some areas are unsuitable for device fabrication, which reduces the maximum yield possible from each wafer. There can also be variations in flatness across the wafer and at local sites, which can affect the focusing of lithographic equipment. When purchasing epitaxial wafers, the buyer must agree on the specifications with the wafer supplier, including the tolerable limits for imperfections. Typically, the more exacting the specification, the more expensive the supplied material.
Epitaxy and doping
When the wafer is prepared, epitaxy creates a crystalline layer of uniform thickness and accurately controlled electrical properties on the wafer surface. The deposited atoms maintain the same structural orientation as the underlying substrate to provide the foundation for building the layered device structures.
The epitaxy is typically grown using chemical vapor deposition (CVD), using a stepped flow process with silicon-based precursor gases. The CVD reactor first heats the wafer temperature to 1600 °C for an etching process to be applied, which takes several minutes. The temperature is then raised again to 1650 °C for epitaxial layer growth. Figure 3 illustrates the temperature profile applied in the reactor.
The precursor gas atoms in CVD adsorb onto the SiC substrate and diffuse along the surface. Chemical reactions lock the atoms in place, and the crystal grows at a rate directly proportional to silicon precursor flow. Introducing chlorine in chlorosilanes, halocarbons, or HCl can accelerate growth. Combined with efficient heating, the growth rate can be as fast as 100µm per hour.
Layer growth is often performed under low-pressure conditions, typically below 100 mbar, which enhances control over the deposition parameters and ensures greater thickness uniformity and purity, reduced defects, and superior coverage. Carbon sources such as propane or halogenated hydrocarbons (CH, Cl) are also used to control the gas phase for precise deposition and carefully manage the carbon-to-silicon ratio to achieve the desired doping. A ratio of about 1:3, carbon to silicon, is usually optimal, depending on the reactor.
Doping, typically with nitrogen for N-type devices and an aluminum-based compound for P-type, tailors the electrical properties by introducing specific elements to the silicon carbide crystal lattice. Precise control over the doping levels is crucial for semiconductor performance.
The results of epitaxial deposition are measured in situ and in real-time, mapping doping concentration across the surface of the wafer and using non-destructive techniques such as spectral reflectance or ellipsometry for thickness characterization. The intelligence gained from these measurements can enable parameter adjustment to ensure the precise control of film thickness, composition, and crystal quality. After epitaxy, annealing processes may be applied to improve the crystal structure and remove defects.
Conclusion
Commercialising SiC has taken a long and intensive engineering effort to overcome the material’s intrinsic challenges and develop repeatable processes for wafer growth and epitaxy. As the world focuses on efficient electrification to achieve sustainability, the solutions developed now enable device manufacturers to meet the growing demands from automotive, renewable energy, and other exciting markets.
