The cost and the physics of fitting more transistors in the space available are showing diminishing returns. The concept of “known good die” is much more difficult to quantify.

For all the talk in the semiconductor industry about trying to reach 1.8 nm process nodes, advanced packaging and its impact on performance seems to be left out. Less than 3% of IC packaging is performed in the United States today.

Additionally, the cost to adopt the most advanced semiconductor node is becoming prohibitive; monolithic advanced node semiconductor processes may not create a strong return on investment in the appropriate amount of time. In response, manufacturers are looking to leverage more functionality from advanced packaging to address these issues.

To help learn more about the process, I’ve provided some answers to questions that illuminate just how vital advanced packaging is to the future of semiconductor performance.

Can you give a high-level overview of the process for packaging?
In the past, packaging was primarily done with wire bonding and surface-mount technology. Today, flip chips (Figure 1) are still the gold standard. The progression of flip-chip integrated circuit (IC) packaging is important.

In its most basic form, IC packaging facilitates the fanout of the semiconductor device interconnects to meet the technology restrictions of the board where the device will reside. Manufacturing constraints of the system-level board prevent ICs from being mounted directly for various reasons, including interconnect density limitations, product reliability concerns, and testing and rework restrictions.

Single or multiple chips are, therefore, placed on the package substrate. This minimizes electrical performance loss, maintaining signal and power integrity while also improving overall reliability. Pairing the silicon chips with specifically designed materials improves reliability by addressing the coefficient of thermal expansion (CTE) mismatch stresses, which can lead to early system-level failure.

Figure 1 shows that since the advent of flip-chip technology, packages have evolved to reduce cost, size, weight, and power (CSWaP). Overall, a smaller footprint lets us do more in less space with less power at a lower cost. This is of particular interest in military and aerospace deployments, which require stringent reliability standards.

As silicon interconnect densities have increased, so have the interconnect densities of high-density-build-up (HDBU) style package substrates. At least to a point. Minimum interconnect densities should bottom out around 125 µm pitch, perhaps slightly lower. This presents an issue in the context of CSWaP because die interconnect densities of 5 µm pitch are already possible.

What has changed in product architecture today to address this?
Historically, when you see advancements in semiconductor performance, it was frequently done through the miniaturization of die through front-end manufacturing improvements and shrinking process nodes. Semiconductors, however, are starting to reach the limit of improvements in front-end manufacturing. Cost is the primary limitation today, but the physics of fitting more transistors in the space available is starting to show diminishing returns. Figure 2 shows how costs have increased as dimensions shrink.

Beginning with single-chip package architecture, increased semiconductor die sizes were the first evolution with monolithic silicon chips. The aim was to do more on one chip in less space. However, larger silicon and more delicate active layers led to reduced product reliability. Those characteristics also increased the difficulty in characterizing the product using existing packaging methods. Silicon turns are also very costly, making this progression unappealing for die sizes approaching 20 mm.

The second architecture iteration was the beginning of what the industry is calling “disaggregation,” or splitting out of various functions into multiple die. The concept of multi-chip modules is not new but is being revisited to support CSWaP objectives. This package style is common in the industry today and facilitates more effective product optimization during development and flexibility down the line. At Tektronix, we have several multi-chip module (MCM) style products from external customers in active production today.

The third iteration, titled 2.5D heterogeneous integration, leverages semiconductor technology and disaggregation to do more in less space by adding another interposer — silicon, glass, silicon carbide — between the substrate and high-density silicon devices or “chiplets.” 2.5D is becoming very important in the industry and is something I could talk about in length, but maybe that’s better for its own interview. My colleague, Brian Hendren, has good insights into this new architecture in an upcoming article.

What challenges arise when working on such a small scale?
Process assembly methodology, while more challenging compared to legacy package designs, is largely understood today. New challenges exist with product design methods, such as software tools and design flow. There are also challenges with thermal solutions, leading to the need to address increasing power densities and electrical test capability. As products become more advanced and disaggregated from a functionality point of view, the concept of “known good die” is much more difficult to quantify.

Chip-to-chip interactions can influence end performance in unpredictable ways, making wafer tests a necessity but bringing challenging cost tradeoffs. End-item product testing is an absolute necessity, but development work is also needed to ensure testing at various stages of assembly is deployed judiciously to ensure proper end-item yield. Design for tests is also an increasing area of focus for these architectures.

What opportunities are there for performance improvement today?
The more we miniaturize packaging and not just the process node, the better the performance we’ll see from the assembled device. The use of interposers will bring about the next evolution in this arena. Shorter electrical connections provide higher bandwidth and lower loss solutions. Disaggregation, or the use of “chiplets,” can facilitate better product characterization and customization. 2.5D architectures can significantly bolster CSWaP initiatives. As you can see, 2.5D packaging is a big focus in the industry today.