The term complementary metal-oxide semiconductor (CMOS) has become a partial misnomer because the dielectric layer that separates gate and source is now rarely a metal oxide. The name persists despite this change.
CMOS refers to pairs of MOSFETs in symmetrical configurations, which in turn are slightly modified FETs. CMOS circuits have become by far the most numerous semiconductors on earth. What makes CMOS devices valuable in electronic equipment is that they are inexpensive, consume (and dissipate) power only during brief switching transitions, and exhibit exceptional noise immunity.
The testing of CMOS circuits is a complex subject that goes far beyond what a single article can cover. Nevertheless, many of the more sophisticated testing schemes rely on a few basic concepts. To understand the basics, it helps to first review how a CMOS device operates.
A single CMOS device consists of two FETs, one P-type and the other N-type, arranged in a symmetrical configuration. The data input is typically applied to the gates and an inverted output extracted from the connected drains. Bias is applied to the sources.
Except during transitions, one of the transistors is off and the other is on. Because they are connected in series with respect to the two power lines, as a pair they do not conduct most of the time. During transitions, however, the power supply is shorted out. Because this event is extremely brief, the amount of power that must be dissipated as heat is minimal. However, the fast rise and fall times create abrupt amplitude spikes which, especially at high frequencies, can be problematic.
When P-type and N-type semiconductors are wired together in pairs as in the CMOS configuration, interesting situations result. A P-type MOSFET exhibits low resistance between source and drain when low voltage is applied at the gate. In contrast, in an N-type MOSFET there is high resistance between source and drain when the gate voltage is high.
In a CMOS device, the opposing MOSFETS work in concert when the two gates are connected together and the two drains are connected together. When the two gates are connected to a high potential, the N-type MOSFET will conduct and the P-type MOSFET will not conduct. In all cases, voltage at the gate determines channel resistance. Because one of the two MOSFETs that are connected in series is almost always off, the assembly as a whole draws only a minute amount of current. There is minimal heat dissipation, so a high device count is feasible within the confines of the small IC.
The CMOS configuration is characterized by two semiconductors that connect in series with respect to the external power supply and connect in parallel with respect to the data input/output. CMOS uses enhancement-mode as opposed to depletion-mode MOSFETs. Enhancement-mode MOFSETs are off, i.e. do not conduct, when gate and source are at the same potential. Depletion-mode MOSFETs are on, i.e. they do conduct, when gate and source are at the same potential.
The outputs of the MOSFETs are considered complementary because when the input is low, the output is high and when the input is high, the output is low. The result of this is that the basic two-FET combination functions as an inverter. A further point to note is that other than during a change in state, the two FETs in the CMOS inverter draw essentially no current.
The latter quality makes possible a technique called Iddq testing, a method for testing CMOS for manufacturing faults. It measures the supply current (Idd) in the quiescent state (when the circuit is not switching). The current consumed in the state is commonly called Iddq for Idd (quiescent), hence the name.
Iddq testing uses the principle that in a correctly operating quiescent CMOS digital circuit, there is no static current path between the power supply and ground, except for a small amount of leakage. Many common semiconductor manufacturing faults (nodes shorted to power or ground, nodes shorted to each other, layer-to-layer shorts, and others) will make the current rise by orders of magnitude, which can be easily detected. Thus a single Iddq test can check the chip for many possible faults. It may also catch faults invisible to conventional testing.
Iddq testing is somewhat more complex than just measuring the supply current. If a line is shorted to Vdd, for example, it draws no extra current if the gate driving the signal is attempting to set it to ‘1.’ But a different input that attempts to set the signal to ‘0’ will show a large rise in quiescent current, signaling a bad part.
One complication with Iddq tests arises as processors shrink: The leakage current grows higher and becomes less predictable. The difference between a low-leakage part with a defect and a naturally high-leakage part is tougher to discern. Also, ever-more-complex ICs imply a single fault will have a lower-percentage effect, making it harder for the Iddq test to detect. To check large ICs, chip designers might use such techniques as power gating, where the entire power supply to sub-blocks can be switched off using a low-leakage switch. This allows testing of each block individually rather than testing a whole chip.
The most conventional CMOS testing techniques involve fault models. The idea is that the possible number and character of defects on a logic chip are too numerous to treat individually. So the approach is to apply a test pattern input to the circuit and record the outputs. Several kinds of chip defect are likely to manifest themselves as the same output pattern, thus indicating a fault.
The example of a stuck-open fault: A fault-free circuit would produce a value at node z equal to the inverse of a or b. The faulty circuit produces a value at z equal to the inverse of a or b or the value a and b and the previous value of z. There are two cases: a = b = 1, z pulled down to 0; and a = 1, b = 0, and z retains the previous state. A test for a stuck-open fault demands the use of two patterns, ab = 00 and ab = 10.
The most common fault model is the stuck-at model. It models defects that cause a single node in the circuit to stick at 1 or at 0. This is not quite true in reality; failures on ICs are often shorts between two conductors or an open in a conductor, and these conditions can cause complicated behavior. Nevertheless, the stuck-at model works well in practice.
The overall measure of logic test regimes is their observability and controllability. Observability refers to how easy it is to observe an internal circuit node by watching what’s on the IC’s output pins. Controllability is the ease of forcing a circuit node to 0 or to 1 by driving the IC’s input pins. Combinational logic is usually easy to observe and control. But finite state machines, such as MPUs and CPUs, can be difficult to observe and control because it may take many cycles to make them enter a desired state.
Ideally, a test pattern would be written such that it would check every node in the chip to prove it isn’t stuck. The goal is to apply the fewest possible test vectors that still check every node. Good observability and controllability reduces the number of test vectors necessary to do this checking.
The exhaustive testing of a circuit like this demands the use of 2M+N patterns for 2M states and 2N transitions from each state.
The problem is that it takes a lot of test patterns to exhaustively check every circuit node. For a circuit with N inputs, it takes 2N patterns to check all possible nodes. N is large for modern-day sophisticated CMOS ICs.
Tests of sequential circuits are even worse. Sequential circuits are those that change state depending values in storage registers. Exhaustive testing requires 2M+N patterns because there are 2M states and 2N transitions from each state. So it takes a sequence of patterns to expose every fault, including an initializing sequence to drive the circuit to a known state, the test itself, and a propagation sequence to propagate the resulting pattern to an observable output.
Consequently, test engineers must use ingenuity to fashion test procedures.
You might extend this to cover more about scan chain and ATPG, to your final points about test coverage and the difficulty of creating adequate test vector sets “by hand”.