At Embedded World 2026 in Nuremberg, Rambus Silicon IP Division Sr. Director of Product Marketing Bart Stevens walked through the company’s newly announced HBM4E Controller IP, targeting the memory bandwidth demands of next-generation AI accelerators, GPUs, and high-performance compute applications.
The headline spec is 16 Gbps per pin, which translates to 4.1 TB/s of throughput per memory device. In an eight-device AI accelerator configuration, that adds up to more than 32 TB/s of memory bandwidth. Stevens framed the announcement in the context of how quickly the HBM standard has been leapfrogging JEDEC baselines from HBM3’s 8 Gbps per pin to 9.6 with HBM3E, back to 8 Gbps but with 2048 pins per device in HBM4, and now scaling pin rates from 12 to 13.2 to 16 Gbps with HBM4E.
“We have a couple of architectural options for our customers to choose from. It is a huge leap because it’s now a doubling of capacity and performance,” said Stevens.
Reliability gets as much attention as raw performance. As memory density and stacking increase, thermal stress becomes a real concern. The Rambus controller includes built-in telemetry and RAS (reliability, availability, and serviceability) features that probe PHY registers for signal-integrity metrics and monitor for single-bit errors, catching degradation trends before they escalate into data loss. Stevens described this deep system visibility as a key differentiator.
For customers designing in the IP, Rambus offers pre-integration and pre-validation with customer-selected PHYs, supporting both 2.5D and 3D packaging configurations. The controller supports AXI and ARM-coherent interfaces and offers options for single- or dual-controller configurations, depending on latency and burst-size requirements. Optional inline memory encryption is available for multi-tenant compute environments where data isolation is a requirement.
Early-access customers are designing with the IP now, and broader availability is expected later this year. The HBM roadmap continues: Stevens noted that HBM5 drafts are in circulation, with an expected focus on data integrity as densities continue to climb.