For years, wide-bandgap semiconductors like GaN and SiC have been positioned as the inevitable successors to silicon, but what if the limits engineers have been bumping up against are less about the material itself and more about how we’ve been designing silicon devices? In this interview with EEWorld, David Jauregui, Co-Founder and Chief Technology Officer of iDEAL Semiconductor, takes a closer look at the “silicon limit,” field shaping, switching and conduction losses, gate-drive requirements, reliability, and its SuperQ device architecture, and making the case for just how much performance silicon may still have left to give.
EEWorld: For at least a decade, the industry has declared silicon dead. What exactly is this “silicon limit” everyone cites, and why does it keep moving?
The ‘silicon limit’ isn’t a fixed physical boundary. It’s the perceived limit of existing device architectures. What many considered material limits often turned out to be architectural limits.
David Jauregui
David Jauregui: The “silicon limit” isn’t a fixed physical boundary. It’s the perceived limit of existing device architectures. Throughout the history of power semiconductors, innovations like trench MOSFETs and superjunction devices have repeatedly redefined what engineers thought was possible with silicon. What many considered material limits often turned out to be architectural limits. As our understanding of device physics and fabrication techniques continues to evolve, so does silicon’s performance potential.
EEWorld: You talk about four pillars: conduction losses, switching losses, cost-performance, and robustness. Does every application really need all four, or should engineers weight them differently depending on what they’re designing?
David Jauregui: Every application has different priorities, but those four pillars are always part of the design equation. A motor drive may place greater emphasis on robustness and peak current capability, while an AI server power supply may prioritize switching performance and efficiency. The challenge is that optimizing one parameter often forces compromises in another. The goal with SuperQ is to give designers more freedom to optimize for their specific application without making those traditional tradeoffs.
EEWorld: On paper, GaN and SiC crush silicon. Bandgap, critical field, all of it. So where do those 10x advantages go by the time the material becomes a device in a real circuit?
Ultimately, the best device is the one that minimizes total system losses, not simply the one with the lowest figure of merit.
David Jauregui
David Jauregui: GaN and SiC offer material advantages, and they’re the right choice for many applications. But designers don’t select products based on material physics alone; they optimize complete power systems in which efficiency, cost, reliability, manufacturability, and ruggedness must be balanced. The best technology depends on the application and where it delivers the most value. Silicon continues to evolve, giving designers access to new levels of performance while preserving the manufacturing ecosystem, design expertise, and infrastructure they are used to.
EEWorld: Engineers got burned learning that datasheet ratings don’t tell the whole story. What should they be asking vendors about avalanche, surge, and gate robustness that never shows up on page one?
David Jauregui: Datasheets are essential, but they can’t capture every aspect of real-world reliability. Engineers should ask how devices behave under high-current avalanche, short-circuit events, gate overstress, and other fault conditions that occur in the application, not just under standardized qualification tests. It’s also worth asking what additional reliability testing the supplier performs beyond industry standards.
EEWorld: RESURF has been around since the 80s, and superjunction broke the so-called silicon limit back in 1999. Walk me through what field shaping actually does in a vertical device, and why it keeps buying silicon more headroom.
David Jauregui: Power MOSFETs rely on a lightly doped region (commonly referred to as the Drift region) to sustain the electric field during the off-state. Because blocking voltage is simply the integral of the electric field over distance—the area under the curve—the device’s voltage rating depends entirely on field shaping. RESURF structures reshape the classical triangular field into a flatter, rectangular profile. This maximizes the area under the curve, allowing the device to block significantly more voltage without exceeding the semiconductor’s critical breakdown field
EEWorld: Switching versus conduction losses has always been the classic trade-off. Which figures of merit actually tell you whether a device improves both, and do they change between hard-switching and soft-switching topologies?
David Jauregui: There isn’t a single figure of merit that tells the whole story because it depends on the switching topology and operating conditions. In hard-switching applications, metrics such as RDS(on), QSW, and output capacitance become increasingly important, whereas soft-switching topologies place greater emphasis on conduction losses and capacitance-related parameters. The key is to evaluate the device in the context of the complete switching event, not just individual datasheet values. Ultimately, the best device is the one that minimizes total system losses, not simply the one with the lowest figure of merit.
EEWorld: Gate drive is where wide-bandgap gets complicated. Five-volt ceilings on GaN, negative rails on SiC. What questions should engineers ask about gate drive before committing to any switch technology, and what do nonstandard drive schemes really cost at the system level?
David Jauregui: Gate drive requirements are an important consideration because they affect the complexity of the overall power stage, not just the switch itself. Engineers should ask what gate voltages are required, whether special protection or bias supplies are needed, and how those requirements impact the driver, PCB layout, EMI, and long-term reliability. Every switch technology has its own design considerations, so it’s important to evaluate the complete system rather than the device in isolation. The best choice is the one that delivers the required performance while fitting the application’s cost, complexity, and reliability objectives.
EEWorld: Most vendors need three or four different platforms to cover the voltage range that SuperQ spans with one. What’s structurally forcing that split for everyone else, and what did you have to change in the device to get from 60 V to 1200 V without starting over each time?
David Jauregui: In a nutshell, this is a cost*performance tradeoff most traditional MOSFET vendors struggle with. For example, a traditional 650V Super Junction MOSFET, which relies on an Epi-Implant architecture, is too expensive to implement at lower-voltage products like 100V MOSFETs. Taking a traditional 100V MOSFET, which relies on a Field-Plate architecture, has worse performance if implemented at higher-voltage products like a 650V MOSFET. SuperQ breaks that relationship, allowing for the same core structure to be used at lower voltages like 60V and higher voltages like 1200V.
EEWorld: Say an engineer wants to drop a SuperQ device into an existing silicon MOSFET socket. How much redesign are they really in for? What carries over, and where do the fast edges force them to rethink layout and gate resistance?
David Jauregui: In many cases, the basic design approach carries over because SuperQ devices are still silicon MOSFETs and use familiar packages, drivers, and gate-drive voltages. That said, anytime you improve switching performance, engineers should revisit the layout, gate resistance, loop inductance, and EMI behavior. Fast edges can expose parasitics that were less visible with slower devices. So it is usually not a complete system redesign, but a validation and optimization of the power loop and gate-drive network in the actual application.
EEWorld: Any new device structure faces the same chicken-and-egg problem: no field history. What reliability and qualification data should engineers demand before designing in something new, and how are you answering that question yourselves?
David Jauregui: Engineers should ask for more than a qualification checkbox; they should ask what stress testing has been done beyond the minimum standard, and how the device behaves under the fault conditions their system will actually see. That means looking at extended HTRB, HTGB, temperature cycling, power cycling, avalanche, gate stress, and short-circuit robustness. At iDEAL, we are addressing that directly by qualifying to AEC-Q101 and extending key reliability tests beyond standard JEDEC requirements, in some cases up to 4x the standard. Also, our devices are 100% UIS screened in production.
About the author
David Jauregui is Co-Founder and Chief Technology Officer of iDEAL Semiconductor, where he leads the development of advanced silicon power MOSFET technologies, including the SuperQ™ architecture. He brings more than 30 years of experience in device architecture, analog and power management IC design, and the commercialization of high-performance semiconductor technologies. Prior to founding iDEAL Semiconductor, he held senior technical and business leadership roles at Texas Instruments, Ciclon Semiconductor, and International Rectifier.