The Fraunhofer IPMS-developed EMSA5-FS processor core for functional safety based on the open-source RISC-V instruction set architecture is supported by another important debug tool. With the integration into the toolsets of the leading manufacturer of microprocessor development tools Lauterbach, numerous debug functions are now available for the 32-bit RISC-V core.
The EMSA5-FS is the first fault-tolerant embedded RISC-V processor core according to functional safety and was awarded the Product of the Year 2022 in the automotive sector by the trade journal Elektronik. Now the developer, the Fraunhofer Institute for Photonic Microsystems IPMS, announced that another important debugger is available for the processor core. The TRACE32 toolset from Lauterbach, the world market leader in hardware-assisted debug tools, now supports the EMSA5-FS and offers developers extensive debug functions.
The EMSA5-FS processor core was the first RISC-V processor core to be certified ASIL-D ready according to automotive functional safety, making it suitable for use in safety-critical in-vehicle systems. It can be made available for any FPGA platform, as well as integrated into customer-specific ASICs for a wide range of foundry technologies. Fraunhofer IPMS also provides services to extend the IP core with customer-specific modules.
Lauterbach’s TRACE32 toolset provides multicore debugging on individual hardware threads of RISC-V cores and enables debugging directly from the reset vector, which is needed to test startup codes and other key functions. Lauterbach also provides high-level assembly debugging for a variety of standard ISA extensions, such as Compressed Instructions and Floating Points. In addition, the JTAG debug transport module (DTM) is fully supported.
The EMSA5-FS is suitable for implementing microcontrollers in automotive, aerospace, medical, and other safety-critical devices and systems.