The MIPI Alliance announced MIPI I3C v1.1, the first update to its innovative interface that eliminates the historical pain points of I2C development. MIPI I3C v1.1, available now to MIPI members, is a scalable, medium-speed, utility and control bus that connects peripherals to an application processor, streamlining integration and improving cost efficiencies in the development of smartphones, wearables, high-performance servers, automotive applications and more.
Relying on a lower number of pins and the smallest amount of PCB real estate compared with other bus solutions, MIPI I3C integrates mechanical, motion, biometric, environmental and any other type of sensor. The new version builds on those capabilities with new features for peripheral command, control and communication to a host processor over a short distance.
For instance, MIPI I3C v1.1 provides for extensible use of extra bus lanes to increase the interface speed to near 100 MHz, future proofing the interface for rising speed requirements. The greater speed support and a host of new features—grouped addressing, enhanced error detection/recovery, slave reset, comprehensive flow control, outside end transfer and new command, control and communication (CCC) capabilities—work together to enable a diverse set of new applications:
- DIMM5 memory control
- “Always-on” imaging
- Server manageability
- Debug application communications
- Touchscreen command and communications
- Sensor device command, control and data transport
- Power management
MIPI will host a webinar on February 12, 2020, at 8 am Pacific to further explore the features and benefits of MIPI I3C v1.1 and provide an update on the I3C ecosystem. To register, please visit http://bit.ly/2t56SVD.
In addition, a variety of other system-solution resources have been introduced to aid developers and support the I3C ecosystem:
- MIPI Discovery and Configuration (MIPI DisCo) for I3Cis a software framework designed to simplify software integration of sensors and other peripherals that use the MIPI I3C device interface, by allowing major operating systems to identify MIPI-conformant external devices in mobile and mobile-influenced systems and automatically implement drivers for them.
- The MIPI I3C Host Controller Interface defines a common set of capabilities for the host controller and the software interface. An update to the interface to support v1.1 is currently in development.
- MIPI Debug for I3C, a bare-metal, minimal-pin interface in development for transporting debug controls and data between a debug and test system (DTS) and target system (TS), is targeted to be released later this year.
- MIPI I3C interoperability workshops and MIPI DevConoffer opportunities to explore device compatibility and learn more about I3C and other MIPI specifications. Check the website frequently for upcoming events.
- Further, a number of information resources, such as FAQs, an Application Note, and a Conformance Test Suite (CTS), are being developed to include v1.1.