Flex Logix Technologies, Inc. announced today a new member of the EFLX4K eFPGA Core Family: the EFLX4K IO eFPGA core. This new core is designed for networking and applications with many heterogeneous processors where customers need to connect very wide buses with relatively small eFPGAs.
“Customers can achieve significant performance advantages when they can connect very wide buses as needed in their designs,” said Geoff Tate, CEO and cofounder of Flex Logix. “While traditional FPGA lacked this flexibility, eFPGA can be easily optimized for various bus sizes, which is critical in networking applications that need as much performance as possible.”
The EFLX4K IO eFPGA core is a derivative of the EFLX4K Logic core optimized for very wide buses. It is available now for implementation on any new process node in about 6-8 months (less where the EFLX4K Logic eFPGA is already implemented). The dimensions of the EFLX4K IO are identical to the EFLX4K Logic and DSP cores to deliver the most flexibility in creating an arrayable solution from a single array (~4K LUT4 equivalents) to at least a 7×7 array (over ~200K LUT4 equivalents). The interconnect network is the same, silicon proven network in the current EFLX4K cores: what changes is that some of the programmable logic is replaced with I/O.
The EFLX4K IO eFPGA core has 1640 inputs and 1640 outputs. This compares to 632 inputs and 632 outputs for the EFLX4K Logic core. The extra inputs and outputs are asymmetrically added all on one side since in typical networking applications the number of input signals are much more than the number of output signals. With the EFLX4K IO eFPGA core, a 1024 bit wide bus can be wired into one side! Wider bus inputs can be handled using multiple EFLX4K IO cores in an array as needed.
The EFLX4K IO can be intermixed in arrays of at least 7×7 with the EFLX4K Logic and DSP cores.
Learn more about the EFLX4K IO from our technologists at DAC, Monday June 25 – Wednesday June 27 at Flex Logix’s booth #2318. Or email us at in…@flex-logix.com