Synopsys, Inc. announced its collaboration with GLOBALFOUNDRIES to develop a broad portfolio of DesignWare IP for GF’s 12LP+ FinFET solution, including USB4/3.2/DPTX/3.0/2.0, PCIe 5.0/4.0/2.1, die-to-die HBI and 112G USR/XSR, 112G Ethernet, DDR5/4, LPDDR5/4/4X, MIPI M-PHY, Analog-to-Digital Converter, and one-time programmable (OTP) non-volatile memory (NVM) IP. The DesignWare IP is optimized to meet the high-bandwidth memory throughput and reliable, high-performance connectivity demands of cloud computing and AI chips implemented on GF’s 12LP+ solution. This recent collaboration marks another significant milestone of the continuous, successful collaboration between the two companies.
GF’s most advanced FinFET solution, 12LP+ builds upon GF’s established 14nm/12LP platform, of which GF has shipped more than one million wafers. Driving the enhanced performance of 12LP+ are features including a 20-percent SoC-level logic performance boost over 12LP, and a 10-percent improvement in logic area scaling.
- The silicon design kit for the DesignWare PCIe 5.0, PCIe 2.1 is available now.
- The silicon design kit for DesignWare USB4/3.2/DPTX/3.0/2.0, PCIe 4.0, LPDDR4X multiPHY, Die-to-Die HBI and 112G USR/XSR, 112G Ethernet, MIPI M-PHY and Analog IP are scheduled to be available in the second half of 2020.
- The silicon design kit for DDR5/4, LPDDR5/4/4X, and the preliminary design kit for DesignWare OTP NVM IP is scheduled to be available in Q1 of 2021.