By John Ferguson, Director of Product Management at Siemens Digital Industries Software
3D ICs extend heterogeneous advanced package technology into the third dimension. They carry the same design to manufacturability challenges as 2D advanced packages, and then some. Although far from mainstream, that time is coming, as chiplet standardization efforts and supporting tool developments begin to make 3D IC practicable and profitable to more players big and small and with smaller production runs.
3D IC enables companies to partition a design and integrate silicon IP at the most appropriate process node and process, providing low latency, high bandwidth data movement, lower manufacturing costs, higher wafer yields, lower power consumption and overall lower costs. These attractive benefits lead to significant growth and development in advanced heterogeneous packaging and 3D IC.
In traditional integrated circuit (IC) design and manufacturing, sign-off strategies are heavily relied upon. Design rule, LVS, and reliability decks are received from a foundry in the form of a process-specific design rule kit. However, this approach does not work for 3D IC advanced heterogeneous packaging, as 3D ICs involve multiple layers with a mix of processes. The conventional thinking that everything on a single layer is coplanar does not hold for 3D ICs, as they involve vertical stacking of components. This creates challenges for semiconductor and IC packaging design engineers in terms of checking interactions between components with different process technologies and determining which interactions to prioritize.
To ensure manufacturability and reliability, we cannot rely on a universal design kit from the foundry or OSAT. Instead, we need to tap into the mind of the 3D IC designer for information. Planning tools are necessary to assist package architects in their floorplanning decisions and provide this information to semiconductor and IC packaging design engineers. This information should include how the components are vertically stacked, rather than just their one-dimensional layout. We must also separate the checking of specific elements from individual layer definitions, as different processes may have different layer numbers for similar structures. This information can be extracted early using a 3D IC prototyping and planning tool.
Planning and floorplanning tools are used to ensure proper alignment and manufacturability of the assembly architecture, which is the traditional role of Design Rule Check (DRC) in the System-on-Chip (SoC) world. However, relying solely on DRC does not guarantee expected functionality. Luckily, Layout Versus Schematic (LVS) analysis can both confirm manufacturability and validate that the layout accurately represents the intended electrical structure and behavior. In contrast to initial work where netlisting and simulation are performed beforehand, LVS compares detailed analyses of all the dies, layers, and devices to ensure they match the intended design. To perform LVS, a source netlist, also known as the “golden netlist,” is required.
However, 3D ICs pose a challenge for LVS due to the presence of interposers, which are commonly passive components that LVS does not work with. Traditional LVS relies on knowing that pins are electrically connected, but passive components lack electrical behavior and do not drive circuit functionality. Additionally, 3D ICs may contain intentionally embedded passive devices such as capacitors, resistors, and photonic elements. Understanding the impact of passive components is necessary and includes knowledge of different wire placements and materials information.
The new components that make 3D IC integration possible introduce new parasitics into the system. These parasitics can impact delay, noise, signal integrity, power, and consequently, the ability to satisfy system design requirements. To understand their impacts, you must accurately and effectively model the parasitics of those components. In addition, higher densities and closer proximity of vertically stacked 3D IC components, like dies and interposers, affect their parasitics.
The choice of extraction methodology and tools depends on the trade-off between performance and accuracy. Higher accuracy requires more complex models and sophisticated tools. Rule-based tools provide high performance, while field solver-based tools offer high accuracy. For TSV parasitics, accurate TSV models can be developed using the foundry’s measurements and internal full-wave solvers. These models can be efficiently inserted during the interconnect parasitic extraction process using rule-based tools. However, rule-based tools struggle with TSV couplings. Parameterized tables can be used for coupling resistance and capacitance, but they have limitations. Full-wave solvers are more accurate but too slow for a large number of TSVs in a real design. Therefore, a specialized field solver that is fast enough for the entire TSV set extraction is the optimal solution.
3D ICs can be implemented using either silicon or organic connectivity, each with its own advantages and challenges. Silicon-based 3D IC structures are implemented using place and route tools, which are good for dense designs but can only handle orthogonal shapes. On the other hand, organic-based 3D IC structures leverage tools similar to traditional PCB-oriented tools.
The choice of technology used impacts the methodologies and tools used for signal integrity analysis. For silicon design, the data flow from place-and-route tools is in GDS format, which lacks the details necessary for traditional signal integrity and electromagnetic (EM) tools. Additional manual steps for extraction can lengthen the analysis process and limit the number of iterations. The data representation also poses challenges and can be time-consuming for electromagnetic extraction However tools used in silicon design for parasitic extraction can mitigate these challenges.
Organic tools, being more PCB-oriented, have more intelligent data, including net names and different structure types, native in the design database. This reduces setup time for parasitic extractions and makes the process less error-prone – pushing extractions and analysis further upstream in the design process, enabling early identification of changes needed in the die-package floorplan based on parasitic impact. Using the right set of analysis capabilities at the right time, designers can make accuracy and performance trade-offs earlier in the process and have confidence in signing off on the total design. This allows them to reap the advantages of 3D IC designs ahead of time.
To learn more download our eBook entitled: Ensuring 3D IC Semiconductor Reliability: Challenges and Solutions for Successful Integration
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