Part 1 of this FAQ looked at the basic issues and topologies related to the challenge of frequency synthesis. Part 2 continues with advanced approaches and their attributes, as well as general concerns when choosing a synthesizer.
Q: Are there other digitally-controlled synthesizer topologies?
A: Yes. A widely used one is called the classical phase lock loop (PLL) integer-N approach (Figure 1). Here, the PLL circuit performs frequency multiplication via a negative feedback mechanism, to generate the output frequency FVCO of the voltage-controlled oscillator (VCO) in terms of the phase-detector comparison frequency, Fr, such that FVCO = N × Fr. This allows the VCO to step through the desired frequencies by changing the value of N and still using a single clock source.
Fig 1: In the PLL integer-N architecture, a phase detector and feedback loop in conjunction with a VCO allow the master clock to be divided into sub-frequency values. (Image source: Texas Instruments)
The output frequency FVCO, that the synthesizer generates can be changed by reprogramming the divider N to a new value. By changing the value N, the VCO can be tuned across the frequency band of interest. The only constraint to the frequency output of the system is that the minimum frequency resolution, or minimum channel spacing, is equal to Fr by this relationship: channel spacing = FVCO/N = Fr.
Q: This is getting complicated; is there more?
A: Absolutely. One of the shortcomings of the classical integer-N PLL approach is that there are issues with what is called phase noise, as well as the relationship between the value of N and the achievable channel spacing, A more complicated topology called the fractional-N approach overcomes this and alters the relationship between N, Fr, and the channel spacing of the synthesizer, to yield frequency resolution that is a fractional portion of the phase detector frequency, see Reference 6.
Q: How is this done?
A: This is accomplished by adding internal circuitry that enables the value of N to change dynamically during the locked state, where the PLL inputs are in phase with each other. If the value of the divider is “switched” between N and N+1 in the correct proportion, an average division ratio can be realized that is N plus some arbitrary fraction, K/F. This allows the phase detectors to run at a frequency that is higher than the synthesizer channel spacing.
Q: There seems to be a lot going on here; is that the case?
A: Yes, indeed, there is a lot going on! But the advantages that these synthesizers offer, especially the fractional-N approach, are so overwhelming that these synthesizers have become the frequency-setting design used in any system which has to tune to a specific channel They are also used for test equipment for steady-state frequency synthesis, sweepable sine-wave sources, and more. A properly designed synthesizer can cover a band of several hundred MHz and even a few GHz with precise frequency steps on the order of 50 kHz, with accuracy determined primarily by one crystal.
Q: What are some of the parameters of interest with digital synthesizers?
A: First, of course, is the range of frequencies to be covered, and next is the needed step size.
Q: That’s all?
A: Absolutely not. Synthesizers in their various forms are complicated, that’s the bad news. But they are extremely amenable to detailed analysis of their performance and weaknesses. Even assuming a perfect clock (crystal) source (which of course doesn’t exist), there are many issues of internal noise, linearity, jitter, spurious frequencies (artifacts near the desired frequency) (Figure 2), and more.
Fig 2: Spurious frequencies (spurs), are undesired spectrum artifacts near the desired signal, and are the result of component and circuit imperfections; they are not the same as harmonics. (Image source: National Instruments)
Q: What are the dynamic issues?
A: The speed at which a synthesizer can be directed to its new output frequency and settle at that value is a concern. There is a tradeoff between switching speed and settling speed, as well as tradeoffs with some other performance capabilities. For applications which require fast switching, such as cellular links and Wi-Fi, where the channel in use changes during the link connection, fast switching and settling are key. Such frequency hopping is used to find and access an unused channel, or in spread-spectrum communications for security (frequency hopping spread spectrum, or FHSS). Some applications will trade slower switching for a higher-purity output.
Q: How do you choose among the many options?
A: Each synthesizer topology has pros and cons among the many parameters. Making the “best” choice involves a careful at priorities, their relative weighting, and available tradeoffs. Fortunately, a synthesizer no longer needs to be custom-designed using small-scale ICs. Due to the wide demand for their synthesized outputs, many vendors offer fully integrated synthesizer as ICs which can develop frequencies from several hundred MHz into the multi-GHz range, with small step sizes on the order of just tens of kHz. For frequencies in the tens of GHz and higher, where a suitable highly integrated IC may not be available, smaller individual function-block ICs are available which can be combined into a larger synthesizer circuit.
Q: Is there any good literature about these synthesizers?
A: The problem is that there is so much useful collateral material about them! There are countless posted articles as well as books ranging from basic tutorials to intense mathematical analysis; References 5 and 6 are just two among the thousands; Reference 7 is the industry’s “bible” on PLLs. (Synthesizers, their many variations, and their performance are like the works of William Shakespeare or James Joyce in that they are a near-infinite source of topics and papers by students, researchers, and vendors.) There are also many papers which look at small variations and enhancements which allows the user to reduce one or more shortcomings such as phase noise.
Synthesizers in their many basic topologies and innumerable variations all forms are among the most-examined topics for research papers, and many of the proposed designs are simulated and analyzed in intense detail. Even though many of these are not necessarily built and tested, the analysis gives insight into the many issues related to synthesizers.
References
- EE World, “Radio receiver architectures, Part 1—TRF and Superhet”
- EE World, “Radio receiver architectures, Part 2—Zero-IF and SDR”
- EE World, “Quartz crystals and oscillators, Part 1: Crystal basics”
- EE World, “Quartz crystals and oscillators, Part 2: Advanced crystals”
- Analog Devices, MT-085 Tutorial, “Fundamentals of Direct Digital Synthesis (DDS)”
- Texas Instruments, Technical Brief SWRA029, “Fractional/Integer-N PLL Basics”
- Floyd M. Gardner, “Phaselock Techniques, Third Edition”
Leave a Reply
You must be logged in to post a comment.